Abstract: Embodiments herein relate to accessing a memory region including confidential information. A memory request from a process may be received. The memory request may include a process ID (PID) of the process, a requested memory address, and a requested access type. The memory request may be compared to a permission set associated with a memory region including the confidential information. Access to the memory region by the process may be controlled based on the comparison.

Abstract: Example embodiments disclosed herein relate to security parameter zeroization. Example embodiments include security parameter zeroization based on a remote security monitor.

Abstract: A security shield assembly has a printed circuit board having a plurality of layers, the plurality of layers including an electrically conductive penetration sensor layer, dielectric layers, and at least one signal layer. An electronic unit is mounted to the printed circuit board and electrically connected to the signal layer.

Abstract: In one implementation, a processor is provided that includes logic to enable a transition from a zeroize state to a clear state. In another implementation, a processor is provided that includes logic to enable a testing secure state, the testing state to enable a testing function; logic to enable a clear state, the clear state to enable a non-secure processing function and to disable a security function; logic to enable a transition from a testing secure state to a clear state; and logic to enable a full secure state, the full secure state to enable the processing function. In another implementation, a processor is provided that includes logic to disable a transition from a clear state to a secure state.

Abstract: Examples disclosed herein relate to secure boot information with validation control data specifying a validation technique. Examples include determining, with the specified validation technique, whether validation data is consistent with the secure boot information.

Abstract: A shift register ring stores bits.

Abstract: A security shield assembly has a printed circuit board having a plurality of layers, the plurality of layers including an electrically conductive penetration sensor layer, dielectric layers, and at least one signal layer. An electronic unit is mounted to the printed circuit board and electrically connected to the signal layer.

Abstract: Example embodiments disclosed herein relate to storing event data and a time value in memory with an event logging module. Example embodiments of the event logging module include event command storage, clock command storage, and memory command storage.

Abstract: Examples disclose a processor with a measurement point to receive an input voltage and a voltage measurer to obtain a first voltage measurement. Further, the examples provide the processor with a switch, based on a signal, to enable a second voltage measurement at the measurement point. Additionally, the processor is to adjust the voltage measurer based on a difference between the first and second voltage measurements.

Abstract: A microcontroller is awakened from a lower power state in response to a trigger indication indicative of a fault condition. After the awakening, the microcontroller performs a security action with respect to secret information in the security module in response to the fault condition.

Abstract: In one implementation, data values having an order are stored at a memory having a plurality of memory locations. Data values are periodically moved between memory locations according to a movement pattern. A selector is synchronized with the movement of the data values according to the movement pattern to select an output.

Abstract: Examples disclosed herein relate to secure boot information with validation control data specifying a validation technique. Examples include determining, with the specified validation technique, whether validation data is consistent with the secure boot information.

Abstract: Embodiments herein relate to cryptographic operations, such as encrypting and/or decrypting information to read from or written to first and second memory regions. The first cryptographic information is related to the first memory region and the second cryptographic information is related to the second memory region.

Abstract: Example embodiments disclosed herein relate to security parameter zeroization. Example embodiments include security parameter zeroization based on a remote security monitor.

Abstract: Embodiments herein relate to accessing a memory region including confidential information. A memory request from a process may be received. The memory request may include a process ID (PID) of the process, a requested memory address, and a requested access type. The memory request may be compared to a permission set associated with a memory region including the confidential information. Access to the memory region by the process may be controlled based on the comparison.

Abstract: Example embodiments disclosed herein relate to reset vectors for boot information. Example embodiments include a clear state reset vector for clear boot information, and a secure state reset vector for secure boot information.

Abstract: Embodiments herein relate to cryptographic operations. A process identifier (PID) identifying a process requesting a cryptographic operation is received. Next, at least one allowed cryptographic operation associated with the PID is determined. Then, the requested cryptographic operation is compared to the at least one allowed cryptographic operation, to determine if the requested cryptographic operation is allowable.

Abstract: In one implementation, a processor is provided that includes logic to enable a transition from a zeroize state to a clear state. In another implementation, a processor is provided that includes logic to enable a testing secure state, the testing state to enable a testing function; logic to enable a clear state, the clear state to enable a non-secure processing function and to disable a security function; logic to enable a transition from a testing secure state to a clear state; and logic to enable a full secure state, the full secure state to enable the processing function. In another implementation, a processor is provided that includes logic to disable a transition from a clear state to a secure state.

Abstract: A memory circuit may include a shift register ring including single-bit shift registers. The circuit may include a clock connected to the shift registers to shift bits within the shift register ring, and a counter connected to the clock and indicating positions of the bits in the shift register ring.

Abstract: A microcontroller is awakened from a lower power state in response to a trigger indication indicative of a fault condition. After the awakening, the microcontroller performs a security action with respect to secret information in the security module in response to the fault condition.