RESET VECTORS FOR BOOT INSTRUCTIONS
Example embodiments disclosed herein relate to reset vectors for boot information. Example embodiments include a clear state reset vector for clear boot information, and a secure state reset vector for secure boot information.
This application claims priority to U.S. provisional patent application No. 61/509,078, filed on Jul. 18, 2011, which is hereby incorporated by reference herein in its entirety.
BACKGROUNDA computing device, such as a device including a processor, may interact with secret or otherwise sensitive information during operation. As such, some computing devices may operate to protect the sensitive information. For example, a computing device may encrypt sensitive information using a security parameter, such as an encryption key, stored on the device. The computing device may also operate to protect the security parameter stored on the device.
The following detailed description references the drawings, wherein:
As noted above, a computing device may operate to protect sensitive information using security parameters stored on the computing device. To protect both the sensitive information and the security parameters, some computing device processors may have multiple operating states that may each be utilized in different stages of the life cycle of the computing device. For example, when a computing device is being developed, tested, and/or initialized in a controlled environment, a processor of the computing device may be operated in a clear state in which the processor provides little or no security for information stored on or utilized by the processor. For example, instructions executed by the processor in this clear state may be stored outside the processor in a cleartext (e.g., unencrypted, uncompressed, etc.) format.
When the computing device is operated in an environment in which it is vulnerable to security threats, the processor may be operated in a secure state in which the device provides more security for information stored on and/or utilized by the processor than in the clear state. For example, instructions and other information used by the processor in the secure state may be stored outside of the processor in an encoded (e.g., encrypted) format to prevent tampering with the information to gain access to security parameters stored on the processor. Additionally, if the computing device detects a breach of the device's security, the processor may zeroize its security parameters and operate thereafter in a zeroize state in which the processor provides event reporting and diagnostic functionalities until the device is returned to the controlled environment. A computing device may store information for each of these state concurrently, but only utilize the information (e.g., execute instructions) for the current state.
A processor having multiple operating states may use a single reset vector pointing to common boot information used to begin the process of booting the computing device, regardless of the desired operating state. This common boot information may include common boot instructions, which may determine the desired operating state for the processor and subsequently cause the processor to read and utilize information (e.g., data and/or instructions) specific to the desired operating state. In such examples, the common boot instructions may additionally determine the format in which the state-specific information is stored and prepare the processor to reformat (e.g., decrypt) the state-specific information, if it is stored in a format other than a default format for the processor. For example, if the common boot instructions determine that the secure state is the desired state, the common boot instructions may then prepare the processor to decrypt any further information read from external while in the secure state.
In such examples, the common boot information to which the reset vector points cannot have multiple different formats at the same time. For example, the common boot information cannot have the cleartext format of a clear state and an encrypted format of a secure state at the same time. Rather, the common boot information may be stored in a default format (e.g., cleartext, unencrypted, etc.) so that the processor may utilize the common boot information (including common boot instructions) immediately after a reset. In such examples, the processor may begin reformatting and using boot information for a given state after the common boot instructions have determined the operating state and prepared the processor to reformat the state-specific boot information.
However, storing common boot information in a default format for the processor, such as cleartext, may be a point of vulnerability for the security of the processor. For example, an attacker may readily modify or replace cleartext boot instructions to thereby cause the processor to enter the wrong operating state. Such altered or replaced instructions may cause the processor to enter a clear state when the common boot instructions would cause the processor to enter the secure state. In such examples, the attacker may be able to gain unauthorized access to security parameters stored on the processor. Additionally, an attacker may learn how to set the state of the processor by viewing instructions, stored in cleartext, for setting the operating state of the processor.
To address these issues, examples disclosed herein include a processor providing separate reset vectors for different operating states of the processor, and providing processor logic-based selection of and reading from one of the reset vectors based on the operating state of the processor. In some examples, each of the reset vectors may point to a first portion of boot information for a different operating state of the processor. In such examples, the boot information for different operating states, including a first piece of boot information accessed for each state, may be stored in different formats. For example, a reset vector for a secure state may point to encrypted boot information and a reset vector for a clear state may point to unencrypted boot information. As such, the use of vulnerable common boot information may be eliminated.
As noted above, examples disclosed herein provide processor logic based selection of and reading from a reset vector. In such examples, logic of the processor may select and read from a reset vector in response to a reset before retrieving any instruction stored outside of the processor. By providing processor logic-based selection of the reset vector, examples disclosed herein may select the reset vector pointing to appropriately formatted boot information for the desired operating state without first loading any instruction stored outside of the processor. For example, processor logic may determine an appropriate reset vector and reformatting method, if any, from an indication of the operating state stored on the processor. In such examples, a processor in the secure state may begin reading and reformatting encoded boot information immediately after a reset request without first reading and utilizing vulnerable common boot instructions to determine the current state and prepare the processor to appropriately reformat state-specific information. As such, all information for the secure state that is stored outside the processor may be stored in an encoded (e.g., encrypted) format, thereby making it more difficult to tamper with information (e.g., instructions) for the secure state to gain access to security parameters stored on the processor.
Referring now to the drawings,
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In some examples, vector controller 120 may receive state value 181 from state storage 112. As used herein, a “vector controller” is a module of a processor including logic on the processor for selecting and reading from one of a plurality of reset vectors based on a state value of the processor, in response to a reset request, without first reading information from outside of the processor. In some examples, the functionality of vector controller 120 may be implemented in the form of electronic circuitry, in the form of executable instructions encoded on a machine-readable storage medium of processor 110, or a combination thereof. In such examples, the vector controller may provide processor logic-based selection of and reading from one of a plurality of reset vectors regardless of how the logic on the processor is implemented.
Additionally, as used herein, a “reset vector” is an address from which a processor may first read or otherwise retrieve information from a machine-readable storage medium outside of the processor after undergoing a reset. As used herein, to read “from” a reset vector means to read information stored at the address of the reset vector or to read information from a sequentially-addressed portion of a storage medium starting at the address of the reset vector. For example, in the context of word-addressed storage (e.g., memory), to read information from a reset vector may be to read the word stored at the address of the reset vector. In other examples, in the context of byte-addressed storage, to read information from a reset vector may be to read a word (e.g., 4 bytes) stored at a plurality of sequentially-addressed bytes of the storage beginning at the address of the reset vector. Additionally, as used herein, information stored “at” a reset vector means information stored at the address of the reset vector or information stored at sequential addresses of a storage medium starting at the address of the reset vector. As used herein, a reset vector may be said to “point to” information stored in a storage medium at the address of the reset vector.
In some examples, the information stored at a reset vector may be an entry address for a set of boot instructions for booting a computing device including the processor. In such examples, the processor may boot the computing device by executing the boot instructions starting with the instructions at the entry address stored at the reset vector. As used herein, an “entry address” is the address of a point of entry into a set of instructions executable by the processor (e.g., a program, etc.). Also, as used herein, a “machine-readable storage medium” may be any electronic, magnetic, optical, or other physical storage to contain or store information such as executable instructions, data, and the like. For example, any machine-readable storage medium described herein may be any of Random Access Memory (RAM), flash memory, a storage drive (e.g., a hard disk), a Compact Disc Read Only Memory (CD-ROM), and the like, or a combination thereof. Further, any machine-readable storage medium described herein may be non-transitory.
In addition to receiving state value 181, vector controller 120 may also receive a reset request 183. In some examples, reset request 183 may be generated by instructions executed by processor 110 (e.g., a software generated reset). In other examples, reset request 183 may be received from outside of processor 110. In response to reset request 183, vector controller 120 may read boot information from one of a plurality of reset vectors selected based on state value 181. As used herein, “boot information” is information that may be used by a processor to boot a computing device including the processor. In some examples, the boot information may include at least one of boot instructions and boot data.
As used herein, “boot instructions” area set of instructions that may be executed by a processor to boot a computing device including the processor. In some examples, a set of boot instructions may be the first instructions executed by the processor after a reset of the processor. Boot instructions may include, for example, instructions for testing and/or configuring components and/or functionalities of the computing device. In such examples, the components of the computing device to be tested and/or configured may include the processor, memory, a memory management unit, cryptographic functionalities, and the like, or a combination thereof. Additionally, as used herein, “boot data” is any data (e.g., addresses, etc.) that may be used by a processor of a computing device, along with boot instructions, to boot the computing device. In some examples, boot data may include an address at which a first instruction of a set of boot instructions is stored in a storage medium outside of the processor. In such examples, a reset vector may point to boot data including an entry address for a set of boot instructions, which may be the address of a first instruction of the set of boot instructions. In such examples, a vector controller 120 may read this boot data (e.g., the entry address for the boot instructions) from a reset vector in response to a reset request.
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If state value 181 indicates a secure state, then, in response to reset request 183, vector controller 120 may read a portion of secure boot information from a secure state reset vector. For example, vector controller 120 may provide, to a machine-readable storage medium storing the secure boot information, a read request 186 to read the portion of the secure boot information from the secure state reset vector. In such examples, the secure state reset vector may be the read address of read request 186. In some examples, the secure boot information may include a set of secure boot instructions and secure boot data. In such examples, the secure boot data may include, for example, an entry address for the secure boot instructions, and this secure boot data may be stored in the storage medium at the address of the secure reset vector. In such examples, the portion of the secure boot information read from the secure state reset vector by vector controller 120 may be secure boot data including the entry address for the secure boot instructions, which may be an address at which one of the secure boot instructions is stored. In some examples, processor 110 may boot the computing device including processor 110 by executing the secure boot instructions beginning with the instruction at the entry address read from the secure state reset vector.
In some examples, vector controller 120 may select one of a plurality of reset vectors in response to reset request 183 by selectively altering an address of a read request generated by processor 110. For example, vector controller 120 may include a core module of processor 110 and, in response to reset request 183, the core module may output a read request having as the read address a default reset vector for the core module (e.g., for an interrupt handler of the core module). In such examples, vector controller 120 may determine that a read address on an address bus of processor 110 refers to a reset region of a machine-readable storage medium, and may selectively substitute at least one region selection bit, set based on state value 181, for at least one bit of the address on the address bus. In this manner, vector controller 120 may selectively alter the address of a read request provided in response to reset request 183 to thereby read from a reset vector associated with state value 181 in response to reset request 183. In other examples, vector controller 120 may select the reset vector in response to reset request 183 in other ways. For example, a core module included in vector controller 120 may receive state value 181 and select one of a plurality of state-specific reset vectors stored in the core module in response to reset request 183. In such examples, the state-specific reset vectors may each be stored in non-volatile storage of the core module or hard-coded in logic of the core module. In such examples, the core module may, in response to reset request 183, output a read request having a reset vector associated with state value 181 as the read address.
In some examples, the clear boot information may have a first format, while the secure boot information has a second format different than the first format. For example, the clear boot information may be stored in a cleartext or an otherwise unencrypted format, while the secure boot information may be stored in an encrypted format. As used herein, information in a “cleartext” format is information that a processor receiving the information is configured to execute or otherwise operate on without first reformatting (e.g., decrypting, decoding, etc.) the instruction. For example, an instruction in a cleartext format may be an instruction that the processor may execute without reformatting, and an address in a cleartext format may be an address from which the processor may read without first reformatting the address. Also, as used herein, information in an “encrypted” format is information in a format that a processor receiving the information may execute or otherwise operate on after decrypting the instruction. Additionally, in some examples, all information for a given state stored outside of processor 110 may have the same format. For example, all information (e.g., data, instructions) that may be utilized by processor 110 in the clear state, including the clear boot information and information and/or executable instructions for other clear state applications, may be stored outside the processor in the same format (e.g., the first format). Additionally, in some examples, all information that may be utilized by processor 110 in the secure state, including the secure boot information and information and/or executable instructions for other secure state applications, may be stored outside the processor in the same format (e.g., the second format).
In some examples, vector controller 120 may include a formatting module that may determine whether to reformat information read from outside of processor 110 based on state value 181. In such examples, when the state value 181 indicates the secure state, the formatting module may decrypt the secure boot instructions read from outside of processor 110. In other examples, the first and second formats may be any two formats different from one another. In some examples, the first and second formats may both be formats other than cleartext. For example, information in the first format may be encrypted or otherwise encoded (e.g., compressed, etc.) in any manner different than the manner in which information in the second format is encrypted or otherwise encoded. In some examples, the first and second formats may be different encrypted formats. In such examples, information in the first and second formats may be encrypted differently (e.g., using different encryption formats and/or different encryption keys, etc.).
In examples described above, a processor may read boot information from different reset vectors based on an operating state of the processor in response to a reset request. By selecting a state-specific reset vector based on the operating state with logic of the processor, the processor may select an appropriate reset vector and begin reading state-specific boot information in response to a reset request before reading any other information from outside of the processor. Additionally, the processor may include a reformatting module to selectively reformat received information based on the operating state of the processor. In such examples, the processor may, in different operating states, process differently formatted instructions beginning with a very first instruction read from outside the processor after a reset. In this manner, examples described herein may eliminate the use of vulnerable, cleartext common boot instructions.
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If state value 181 indicates the secure state, vector controller 120 may, in response to reset request 183, provide read request 186 to storage medium 250 to read a portion of secure boot information 254 having the second format from a secure state reset vector. In some examples, the portion of secure boot information 252 read from the secure state reset vector may be secure boot data 255A, which may include an entry address for secure boot instructions 255B. In such examples, processor 110 may boot a computing device including processor 110 with secure boot instructions 255B after reading secure boot data 255A from the secure state reset vector. For example, after reading secure boot data 255A from the secure state reset vector, processor 110 may begin executing secure boot instructions 255B beginning with a secure boot instruction stored at the entry address stored at the secure state reset vector.
In some examples, prior to executing secure boo instructions 255B, processor 110 may verify that secure boot information 254 has not been altered by checking at least some of secure boot information 254 against validation data, such as a digital signature, of secure boot information 254. As used herein, “validation data” may be any type of data that may be derived from a collection of information and subsequently used to determine whether the information has been altered since generation of the validation data. In some examples, at least some of secure boot information 254 may be stored on processor 110 (e.g., in a cache) until processor 110 verifies that validation data derived from the stored information matches the validation data included in the secure boot information 254. In some examples, the verification data may be derived using hashing, processes used for error detection (e.g., processes used to generate a checksum, a cyclic redundancy check (CRC), etc.), or the like. If the derived validation data matches the validation data of boot information 254, the instructions may be executed, and otherwise not. In some examples, any state-specific information stored on storage medium 250 may include validation data for the information, and processor 110 may verify the validation data prior to utilizing some or all of the information.
In some examples, vector controller 120 includes a core module 222 and a formatting module 225 including an encryption module 227. In such examples, the functionalities of modules 222, 225, and 227 may be implemented in the form of electronic circuitry, in the form of executable instructions encoded on a machine-readable storage medium, or a combination thereof. In some examples, core module 222 may include or implement the functionalities of a CPU core. As used herein, a “CPU core” is a component of a processor capable of at least executing instructions. In some examples, a CPU core may include at least one of an arithmetic logic unit (ALU), an interrupt handler, a fetch controller, a data write-back controller, a floating-point unit, or a combination thereof. In some examples, core module 222 may execute or otherwise operate on information having the first format without this information first being reformatted. For example, core module 222 may execute instructions having the first format and may operate on data (e.g., addresses) having the first format. In some examples, the first format may be a cleartext format.
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Additionally, in some examples, information used by processor 110 in the secure state, including at least secure boot information 254, for example, may be stored outside of processor 110 in the second format. As such, information 287 read from storage medium 250 when processor 110 is in the secure state (e.g., secure boot information 254) may have the second format. Accordingly, in some examples, formatting module 225 may reformat information 287 received from storage medium 250 from the second format to the first format, if state value 181 indicates the secure state.
In some examples, formatting module 225 may include an encryption module 227 to encrypt and decrypt information. In such examples, the second format may be an encrypted format for protecting the information for the secure state when stored outside of processor 110, and the first format may be an unencrypted format, such as a cleartext format. In such examples, encryption module 227 may decrypt received information 287 from an encrypted second format to the unencrypted first format, if state value 181 indicates the secure state. In examples described herein, storing information used in the secure state in an encrypted format when stored outside of processor 110 may provide additional security for the secure state of processor 110. For example, the information may be kept secret when stored outside of the processor when stored in an encrypted format. Additionally, it may be difficult to effectively replace or modify sections of code stored in an encrypted format.
Additionally, in some examples, if state value 181 indicates the secure state, formatting module 225 may reformat information 289 to be written to storage medium 250 from the first format to the second format (e.g., encrypt the information) before writing the information. In such examples, if the information written is subsequently read by processor 110 in the secure state, then formatting module 225 may reformat the information from the second to the first format.
By selecting an operating mode based on a state value 181 of state storage 112, formatting module 225 may allow all information utilized by a processor in a given mode to be stored outside of the processor in a state-specific format. For example, all information for the clear state, including the information stored at the clear state reset vector, may be stored in first format (e.g., a cleartext format), while all information for the secure state, including the information stored at the secure state reset vector, may be stored in a second format (e.g., an encrypted format). In such examples, formatting module 225 may correctly reformat (or bypass) all information read in a given operating state of the processor, beginning with information read from a state-specific reset vector, based on state value 181. In this manner, examples disclosed herein may eliminate the use of common boot information, and instead allow state-specific boot information to be used in each operating state. Further, in some examples, the state-specific boot information for different states may have different, state-specific formats.
Additionally, in some examples, the operating states of processor 110 may include a zeroize state in addition to the clear and secure states. In such examples, the operating state of processor 110 may be the zeroize state when state storage 112 stores a zeroize state value, different that the clear and secure state values, as state value 181. As used herein, a “zeroize state” of a processor may be a state entered by the processor after detection of a security incident and in which the processor prevents the storage of security parameters and permits diagnostic functionalities of the processor. Additionally, in some examples, a processor in the zeroize state may permit event reporting functionalities, but permit few or no security functionalities of processor 110.
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In some examples, zeroize boot information 256 may have a third format different than the first and second formats. In such examples, zeroize boot information 256 may be encoded, encrypted, or otherwise formatted differently than clear and secure boot information 252 and 254. For example, when clear boot information 252 is in a cleartext format, and secure boot information 254 is encrypted, zeroize boot information 256 may be encrypted differently than secure boot information 254 (e.g., encrypted with a different key or by a different process), or may be compressed or otherwise encoded by a suitable process other than encryption. In other examples, the first, second, and third formats may be any three formats different from one another. In some examples, all three formats may be formats other than cleartext. For example, information in the first, second, and third formats may each be encrypted, encoded, or otherwise formatted such that the three formats are different from one another.
In some examples, information used by processor 110 in the zeroize state, including at least zeroize boot information 256, for example, may be stored outside of processor 110 in the third format. In such examples, information 287 read from storage medium 250 when processor 110 is in the zeroize state (e.g., zeroize boot information 256) may have the third format. Accordingly, in some examples, formatting module 225 may reformat information 287 received from storage medium 250 from the third format to the first format, if state value 181 indicates the zeroize state. In such examples, formatting module 225 may have multiple formatting modes. For example, formatting module 225 may operate in a first formatting mode to reformat information from the second to the first format, if state value 181 indicates the secure state. Additionally, formatting module 225 may operate in a second formatting mode to reformat information from the third to the first format, if state value 181 indicates the zeroize state. In other examples, zeroize boot instructions 256 may have the same format as clear boot instructions 252 (i.e., the first format). In such examples, formatting module 225 may enter a bypass mode if state value 181 indicates the zeroize state. In some examples, vector controller 120 may select one of the plurality of reset vectors in response to reset request 183 in any manner described above in relation to
Additionally, in some examples, all information for a given state stored outside of processor 110 may have the same format, as described above in relation to
In some examples, storage medium 350 may include clear boot information 252 and secure boot information 254, as described above in relation to
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In some examples, in response to reset request 183, vector controller 120 may provide a read request 384 to storage medium 350 to read a portion of clear boot information 252 from a clear state reset vector, if state value 181 indicates the clear state. The read address of read request 384 may be the clear state reset vector. In some examples, the portion of clear boot information 252 read from the clear state reset vector may be clear boot data 253A, which may include an entry address for clear boot instructions 253B. In such examples, processor 110 may boot computing device 300 with clear boot instructions 253B after reading clear boot data 253A from the clear state reset vector, as described above in relation to
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In some examples, vector controller 120 may include formatting module 225, as described above in relation to
Additionally, in some examples, all information for a given state stored outside of processor 110 may have the same format, as described above in relation to
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In some examples, storage control module 332 may control interaction with secure parameter storage 334 in accordance with the operating state of processor 310. In the example of
Additionally, in some examples, storage control module 332 may prevent information, such as security parameters, from being written to secure parameter storage 334 if state value 181 indicates the zeroize state. For example, storage control module 332 may detect an operation to write to secure parameter storage 334. If state value 181 indicates the clear or secure state, storage control module 332 may take no action to prevent the write operation. If state value 181 indicates the zeroize state, storage control module 332 may prevent the write operation by, for example, preventing a write control signal from being asserted or by causing a processor exception to prevent the write operation.
In some examples, security control module 340 may control the response of processor 310 to a security incident based on the operating state of processor 310. In the example of
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If state value 181 indicates the clear state, then record storage module 344 may store an incident record in response to incident monitor module 342 detecting a security incident. In such examples, record storage module 344 may store the incident record in record storage on or external to processor 310. The incident record may include details of the security incident, such as the date, time, event that triggered the detection of the security incident, and any other details that may be used to diagnose, study or further determine the cause of the security incident. Additionally, security control module 340 may prevent zeroize module 346 from zeroizing of any parameter of secure parameter storage 334 if state value 181 indicates the clear state. In this manner, processor 310 may be tested in the clear state without zeroizing secure parameter storage 334, which may also be written with security parameters as part of an initialization process in the clear state. In such examples, the ability of incident monitor module 342 to detect security incidents may be tested without zeroize module 346 zeroizing secure parameter storage 334 upon detecting a security incident.
If state value 181 indicates the zeroize state, then, in response to incident monitor module 342 detecting a security incident, indication module 348 may indicate the occurrence of the security incident. In some examples, indication module 348 may output at least one of an auditory indication, visual indication, or other indication to a user of computing device 300 via an output device (e.g., display, speaker, etc.) of computing device 300 to indicate the occurrence of the security incident. Additionally, in some examples, security control module 340 may prevent record storage module 344 from recording any incident records if state value 181 indicates the zeroize state. In this manner, security control module 340 may alert a user to the detection of a security incident while preventing record storage module 344 from overwriting an incident record documenting the security incident that caused processor 310 to enter the zeroize state.
As noted above, each of the operating states of processor 310 may cause processor 310 to operate in a manner appropriate for a different stage of the life cycle of computing device 300. For example, as described above in relation to
Additionally, in some examples, the secure state may dictate that processor 310 permit certain security functionalities prevented in the clear state. For example, the secure state may dictate that processor 310 reformat all information read from or written to external storage and at least partially zeroize secure parameter storage 334 in response to detecting a security incident. The secure state may also permit writing information to secure parameter storage. Moreover, in some examples, the zeroize state may dictate that processor 310 prevent writing to secure parameter storage 334 and output an indication in response to detecting a security incident rather than storing an incident record. As such, the clear, secure, and zeroize states may each cause processor 310 to operate in a manner appropriate to a different portion of the life cycle of computing device 300. Also, while examples are described herein in the context of clear, secure, and zeroize states, other examples may include additional and/or other states.
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In some examples, interrupt handler 324 may receive reset request 183 and, in response, may provide a memory access address 375 on an address bus 370 of processor 310 as part of a read operation. In some examples, the read operation may be a request to read from a default reset vector of interrupt handler 324, and memory access address 375 may be the address of the default reset vector. The read operation may include memory access address 375 and a read control signal 376 to indicate a read operation to storage medium 350. In some examples, address bus 370 may have first and second bus sections 372 and 374, which may provide first and second portions of an address on address bus 370, respectively, to address selector 326. In such examples, first bus section 372 includes less than all of an address on bus 370, and second bus section 374 includes at least one bit of the address. Address bus 370 may provide the first portion of an address on address bus 370 to storage medium 350 via first bus section 372.
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In some examples, if module 328 determines from the first portion of address 375 that address 375 refers to reset region 360, then selection bits determining module 329 may set region selection bits 394 based on state value 181. In such examples, address selector 326 may provide the region selection bits 394 to storage medium 350 in place of the second portion of the memory access address output by interrupt handler 324. In this manner, address selector 326 may substitute region selection bits 394 for the second portion of address 372 if address 375 refers to reset region 360, in order to redirect the read request to a reset vector associated with state value 181 (i.e., the operating state of processor 310). If module 328 determines from the first portion of address 375 that address 375 does not refer to reset region 360, then module 329 may set region selection bits 394 equal to the second portion of address 375 received via second bus section 374. In this manner, storage medium 350 may receive the read request output by interrupt hander 324 if address 375 does not refer to reset region 360.
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In some examples, a default reset vector of a processor (e.g., of an interrupt handler of the processor) may be an address pointing to the beginning of a last word (e.g., a last 4 bytes) of addressable memory. For example, the default reset vector may be the hexadecimal address 0xFFFF FFFC, which points to the first of 4 sequentially stored bytes of memory that form the last word of addressable memory. In the example of
In some examples, the clear reset vector may be the address 0xFFFF FFFC, the secure reset vector may be the address 0xFFFF FFF8, and the zeroize reset vector may be the address 0xFFFF FFF4. In such examples, reading information from one of these reset vector may include reading 4 sequentially stored bytes beginning at the address of the reset vector. Additionally, in such examples, as the clear reset vector may be the same address as the default reset vector, and the 4 bytes beginning at 0xFFFF FFF0 may be unused.
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In some examples, selection bits determining module 329 may include a multiplexer 438 and two inverters 434 and 436. In such examples, multiplexer 438 may receive region signal 435, address bits A2 and A3 of second bus section 374, and the respective outputs of inverters 434 and 436. Multiplexer 438 may output region selection bits 394. In some examples, multiplexer 438 may set region selection bits 394 based on address bits A2 and A3 if region signal 435 is a logic 0, indicating that address 375 does not refer to reset region 360. In such examples, multiplexer 438 may output address bits A2 and A3 to storage medium 350 (of
In some examples, multiplexer 438 may set region selection bits 394 based state value 181, if region signal 435 is a logic 1, indicating that memory access address 375 refers to reset region 360. In some examples, state value 181 is stored as one or more bits in state storage 112 (of
In the example of
In such examples, when state value 181 indicates the clear state, multiplexer 438 may output “11” as region selection bits 394, to cause vector controller 120 (of
In this manner, address selector 326 may detect a read operation having a read address referring to reset region 360, such as a request to read a default reset vector, and redirect the read request to a state-specific reset vector based on state value 181. Additionally, address selector 326 may allow addresses not referring to reset region 360 to be provided to storage medium 350 (of
In the example of
Additionally, in other examples, address selector 326 may be used to substitute region selection bits for different address bits. For example, second bus section 374 may include address bits A12 and A13, while first bus section 372 includes the remaining address bits. In such examples, reset region 360 may be the last 16 kilobytes (KB) of storage medium 350, with each of the three operating states having a full 4 KB block assigned to it (with one 4 KB block being unused). Such examples may be implemented in a manner similar to the example illustrated in
In other examples, a different computing device architecture may be utilized. For example, examples described herein may be implemented with a word-addressed memory using 20-bit addresses. In such examples, a vector controller may use an address selector similar to address selector 326 of
At 505 of method 500, vector controller 120 of processor 110 may receive a state value 181 from state storage 112. In some examples, state value may indicate one of a plurality of operating states of processor 110. For example, the operating states may include a clear state associated with a clear state reset vector pointing to clear boot information, a secure state associated with a secure state reset vector pointing to secure boot information, and a zeroize state associated with a zeroize state reset vector pointing to zeroize boot information. In some examples, the secure boot information may have a different format than the clear boot information, as described above in relation to
At 510 of method 500, vector controller 120 may receive reset request 183. In the example of
At 520 of method 500, processor 110 may boot the computing device including processor 110 based on state value 181 indicating the clear state and based on information stored at the reset vector associated with state value 181. As used herein, a given reset vector is “associated with” a given operating state of a processor if the processor is to read from the given reset vector in response to a reset vector when it is in the given operating state. In some examples, processor 110 is to read from a clear state reset vector when state value 181 indicates the clear state. In such examples, at 520, processor 110 may boot the computing device based on a portion of clear boot information (e.g. clear boot data) stored at the clear state reset vector, as described above in relation to
At 530 of method 500, processor 110 may boot the computing device based on state value 181 indicating the secure state and based on information stored at a secure state reset vector associated with the secure state value. In such examples, at 530, processor 110 may boot the computing device based on a portion of secure boot information (e.g., secure boot data) stored at the secure state reset vector, as described above in relation to
At 605 of method 600, vector controller 120 of processor 110 may receive a state value 181 from state storage 112. In some examples, state value may indicate a clear state associated with a clear state reset vector pointing to clear boot information, a secure state associated with a secure state reset vector pointing to secure boot information, or a zeroize state associated with a zeroize state reset vector pointing to zeroize boot information. In the example of
At 610 of method 600, vector controller 120 may receive reset request 183. In the example of
At 620 of method 600, processor 110 may boot the computing device based on state value 181 indicating the clear state and based on information stored at a clear state reset vector associated with the clear state value. In such examples, at 620, processor 110 may boot the computing device based on a portion of clear boot information (e.g., clear boot data) stored at the clear state reset vector, as described above in relation to
At 640 of method 600, processor 110 may boot the computing device based on state value 181 indicating the secure state and based on information stored at a secure state reset vector associated with the secure state value. In such examples, at 640, processor 110 may boot the computing device based on a portion of secure boot information (e.g., secure boot data) stored at the secure state reset vector, as described above in relation to
After booting with the secure boot information, method 600 may proceed to 645, where processor 110 may zeroize the security parameter stored in the secure parameter storage of processor 110 in response to a security incident. In some examples, processor 110 may monitor processor 110 and/or the computing device including processor 110 for security incidents, as described above in relation to
At 655 of method 600, processor 110 may boot the computing device based on state value 181 indicating the zeroize state and based on information stored at a zeroize state reset vector associated with the zeroize state value. In such examples, at 655, processor 110 may boot the computing device based on a portion of zeroize boot information (e.g., zeroize boot data) stored at the zeroize state reset vector, as described above in relation to
After booting with the zeroize boot information, method 600 may proceed to 660, where processor 110 may perform at least one fault diagnostic operation. In some examples the operation may be performed to investigate a security incident that caused processor 110 to enter the zeroize state. In such examples, the operation may include analyzing and/or outputting at least one incident record stored in record storage by processor 110 when processor 110 was in the clear or secure state. In some examples, the operation may be implemented in the form of executable instructions encoded on a machine-readable storage medium, in the form of electronic circuitry, or a combination thereof.
Claims
1. A processor comprising:
- state storage to store a state value indicating an operating state of the processor; and
- a vector controller to: read, from a clear state reset vector, a portion of clear boot information having a first format in response to a reset request, if the state value indicates a clear state; and read, from a secure state reset vector, a portion of secure boot information having a second format in response to the reset request, if the state value indicates a secure state, wherein the first and second formats are different.
2. The processor of claim 1, wherein the clear boot information includes clear boot instructions of the first format, the secure boot information includes secure boot instructions of the second format, and wherein the vector controller comprises:
- a core module to operate on information having the first format; and
- a formatting module to: receive information from a storage medium; reformat the received information to the first format, if the state value indicates the secure state; reformat information to be written to the storage medium from the first format to the second format, if the state value indicates the secure state; and output the received information in the format in which it was received, if the state value indicates the clear state.
3. The processor of claim 2, wherein:
- the first format is an unencrypted format;
- the second format is an encrypted format; and
- the formatting module further comprises: an encryption module to decrypt the received information, if the state value indicates the secure state.
4. The processor of claim 2, wherein the vector controller is further to:
- read, from a zeroize state reset vector, a portion of zeroize boot information in response to the reset request, if the state value indicates a zeroize state, wherein the zeroize boot information includes zeroize boot instructions.
5. The processor of claim 4, wherein:
- the zeroize boot information has a third format different from the first and second formats;
- the formatting module is further to reformat the received information from the third format to the first format, if the state value indicates the zeroize state; and
- the secure boot information includes validation data.
6. A computing device comprising:
- a processor comprising: state storage to store a state value indicating an operating state of the processor; and a vector controller to: read, from a clear state reset vector, a portion of clear boot information in response to a reset request, if the state value indicates a clear state; read, from a secure state reset vector, a portion of secure boot information in response to the reset request, if the state value indicates a secure state; and read, from a zeroize state reset vector, a portion of zeroize boot information in response to the reset request, if the state value indicates a zeroize state, wherein the clear boot information, the secure boot information, and the zeroize boot information are each independent from one another.
7. The computing device of claim 6, further comprising:
- a machine-readable storage medium encoded with instructions executable by the processor, the storage medium comprising the clear boot information including clear boot instructions, the secure boot information including secure boot instructions, and zeroize boot information including zeroize boot instructions; and
- wherein the processor further comprises: a storage control module to: prevent information from being written to the secure parameter storage, if the state value indicates the zeroize state; and permit information to be written to the secure parameter storage, if the state value indicates the clear state or the secure state.
8. The computing device of claim 7, wherein the processor further comprises:
- a security control module to: monitor the processor for security incidents; store an incident record in response to detecting a security incident, if the state value indicates the clear state; zeroize the secure parameter storage in response to detecting the security incident, if the state value indicates the secure state; and indicate the occurrence of the security incident in response to detecting the security incident, if the state value indicates the zeroize state.
9. The computing device of claim 6, wherein:
- the clear and zeroize boot information has a first format;
- the secure boot information has a second format different than the first format; and
- the processor comprises a formatting module to reformat the read information from the second format to the first format, if the state value indicates the secure state.
10. The computing device of claim 6, further comprising:
- an address bus to: provide a memory access address having first and second portions to an address selector of the vector controller; and provide the first portion of the memory access address to the storage medium;
- wherein the address selector is to: receive the memory access address; and provide, to the storage medium, region selection bits, set based on the state value, as the second portion of the memory access address, if the memory access address refers to a reset region of the storage medium.
11. The computing device of claim 10, wherein:
- the vector controller further comprises: an interrupt handler to provide the memory access address on the address bus as part of a read operation in response to the reset request; and
- the address selector comprises: a region determining module to perform an AND operation on at least a portion of the first portion of the memory access address to determine whether the memory access address refers to the reset region; and a multiplexer to set the region selection bits based on the state value, if the region determining module indicates that the memory access address refers to the reset region.
12. The computing device of claim 11, wherein:
- the reset region of the storage medium comprises a clear region including at least the portion of clear boot information, a secure region including at least the portion of the secure boot information, and a zeroize region including at least the portion of the zeroize boot information; and
- wherein the region selection bits distinguish among addresses in at least the clear region, the secure region, and the zeroize region, if the first portion of the memory access address refers to the reset region.
13. A method comprising:
- receiving, from state storage, a state value indicating one of a plurality of operating states of a processor, the operating states including a clear state associated with a clear state reset vector pointing to clear boot information, a secure state associated with a secure state reset vector pointing to secure boot information having a different format than the clear boot information, and a zeroize state associated with a zeroize state reset vector pointing to zeroize boot information; and
- booting, in response to a reset request, a computing device including the processor with the clear, secure, or zeroize boot information based on the state value and information stored at the reset vector associated with the state value, wherein the clear boot information, the secure boot information, and the zeroize boot information are independent from one another.
14. The method of claim 13, further comprising:
- receiving a security parameter with the processor, if the computing device is booted with the clear boot information;
- storing the received security parameter in parameter storage of the processor, if the computing device is booted with the clear boot information;
- zeroizing the security parameter in the parameter storage in response to a security incident, if the computing device is booted with the secure boot information;
- performing a fault diagnostic operation, if the computing device is booted with the zeroize boot information.
15. The method of claim 13, wherein:
- booting the computing device with the clear boot information comprises reformatting the clear boot information from a first format to a cleartext format;
- booting the computing device with the secure boot instructions comprises reformatting the secure boot information from a second format to a cleartext format, wherein the first and second formats are different; and
- booting the computing device with the zeroize boot information comprises reformatting the zeroize boot information from a third format to a cleartext format, wherein the third format is different than the first and second formats.
Type: Application
Filed: Dec 15, 2011
Publication Date: May 29, 2014
Inventor: Ted A. Hadley (Sunnyvale, CA)
Application Number: 14/233,310
International Classification: G06F 21/57 (20060101); G06F 1/24 (20060101);