Abstract: The present invention relates to a method for depositing metal layers on substrates with improved surface morphology. According to one aspect of the invention, a metal is deposited by chemical vapor deposition on a substrate having an aperture formed therein. A metal is then deposited on the substrate by physical vapor deposition performed with a low substrate temperature. The substrate is then heated. The substrate may then receive a metal deposited by physical vapor deposition performed at a high temperature and an additional heating step. The aperture of the resulting substrate is filled with metal and is substantially void-free and has a smooth surface morphology.

Abstract: A refractory metal layer is deposited onto a substrate having high aspect ratio contracts or vias formed thereon. Next, a plasma-enhanced CVD refractory metal nitride layer is deposited on the refractory metal layer. Then, a metal layer is deposited over the metal nitride layer. The resulting metal layer is substantially void free and has reduced resistivity, and has greater effective line width. Plasma-enhanced chemical vapor deposition of the metal nitride layer comprises forming a plasma of a metal-containing compound, a nitrogen-containing gas, and a hydrogen-gas to deposit a metal nitride layer on a substrate. The metal nitride layer is preferably treated with nitrogen plasma to densify the metal nitride film. The process is preferably carried out in an integrated processing system that generally includes various chambers so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without exposure to possible contaminants.

Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

Abstract: The present invention provides a method for filling an aperture on a substrate by depositing a metal film on the substrate of insufficient thickness to fill the sub half-micron aperture and then annealing the substrate in a low pressure chamber at a temperature below a melting point of the deposited metal film. The present invention further provides forming a planarized film over the void-free aperture by physical vapor depositing a metal film over the annealed film.

Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

Abstract: A method for metallizing integrated circuits is disclosed. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from the group of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof. The liner material is preferably conformably deposited on the substrate using physical vapor deposition (PVD). The one or more metal layers are deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.

Abstract: A contact level via and a method of performing selective deposition of a barrier layer to form a contact level via for selective aluminum metallization. Specifically, the method forms a self-aligned silicide region by depositing titanium atop a structure containing a contact level via, converting the titanium in the contact regions into titanium silicide, removing the unreacted titanium, and performing nitridation of the titanium silicide to complete a barrier layer located in only the contact region of the via. Once the barrier layer is formed, the layer can be optionally fortified through oxygen stuffing to create an effective barrier layer for aluminum metallization.

Abstract: A method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate that can compensate for some misalignment between the filled vias and the lines. By alternately depositing liner-barrier layers and aluminum layers on the substrate, different etch chemistries can be used that can anisotropically etch an aluminum layer used to form the lines without etching voids in the aluminum-filled vias.

Abstract: The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectic layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized.

Abstract: The present invention is an apparatus and method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal is then deposited onto the substrate and grows selectively in the contact hole or via where a barrier layer serves as a nucleation layer. The process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.

Abstract: The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectric layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized.

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.

Abstract: A contact level via and a method of performing selective deposition of a barrier layer to form a contact level via for selective aluminum metallization. Specifically, the method forms a self-aligned silicide region by depositing titanium atop a structure containing a contact level via, converting the titanium in the contact regions into titanium silicide, removing the unreacted titanium, and performing nitridation of the titanium silicide to complete a barrier layer located in only the contact region of the via. Once the barrier layer is formed, the layer can be optionally fortified through oxygen stuffing to create an effective barrier layer for aluminum metallization.

Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

Abstract: The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power.

Abstract: The present invention provides a method and apparatus for forming an interconnect with application in small feature sizes (such as quarter micron widths) having high aspect ratios. Generally, the present invention provides a method and apparatus for depositing a wetting layer for subsequent physical vapor deposition to fill the interconnect. In one aspect of the invention, the wetting layer is a metal layer deposited using either CVD techniques or electroplating, such as CVD aluminum (Al). The wetting layer is nucleated using an ultra-thin layer, denoted as .di-elect cons. layer, as a nucleation layer. The .di-elect cons. layer is preferably comprised of a material such as Ti, TiN, Al, Ti/TiN, Ta, TaN, Cu, a flush of TDMAT or the like. The .di-elect cons. layer may be deposited using PVD or CVD techniques, preferably PVD techniques to improve film quality and orientation within the feature. Contrary to conventional wisdom, the .di-elect cons.

Abstract: The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free.

Abstract: The present invention relates generally to an improved apparatus and process to provide a thin self-aligning layer prior to forming a conducting film layer thereover to improve the film characteristics and deposition coverage. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by either vapor deposition or chemical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. In another aspect of the invention, a thin, self-aligning layer is formed over a barrier layer prior to deposition of a conducting film thereover.

Abstract: The present invention generally provides a method of forming a structure having a selective CVD metal plug with a continuous barrier layer formed thereon. More particularly, the present invention applies a thin layer of warm PVD metal over a selective CVD metal plug and adjacent nodules on the dielectric field to planarize the metal surface. A barrier is then deposited over the planarized metal surface. Therefore, the invention provides the advantages of having (1) void-free, sub-half micron selective CVD metal via plugs and interconnects, and (2) a reduced number of process steps without the use of CMP, and (3) barrier layers over the metal plugs to improve the electromigration resistance of the metal.