Patents by Inventor Ted White

Ted White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190188753
    Abstract: Disclosed in some examples are systems, methods, devices, and machine-readable mediums for providing information about the actual viewing audience of an online advertisement. When an online advertisement is displayed to a viewer, the online advertisement image may contain a tracking pixel pointing to a system which, when retrieved, causes a data object to be installed on the viewer's computer. Later, the viewer may return to the system as part of participation in an otherwise unrelated online survey. The system may recognize the data object, and insert questions related to the online advertisement in the survey.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 20, 2019
    Inventors: Ted McConnell, Joseph Zahtila, Jessey White-Cinis, Brett Schnittlich
  • Publication number: 20070272952
    Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
    Type: Application
    Filed: August 10, 2007
    Publication date: November 29, 2007
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Voon-Yew Thean, Brian Goolsby, Linda McCormick, Bich-Yen Nguyen, Colita Parker, Mariam Sadaka, Victor Vartanian, Ted White, Melissa Zavala
  • Publication number: 20070257322
    Abstract: A topography (40) is provided which includes a device having a transistor formed from a stack of semiconductor layers (42/46). The different semiconductor layers are spaced apart by a gate (60) and by support structures (48) comprising a material having different etch characteristics than the materials of the spaced apart semiconductor layers. The device includes a first transistor channel (76) within the upper semiconductor layer and, in some cases, further includes a second transistor channel within the lower semiconductor layer. The resulting hybrid transistor structure may be fabricated as one of a pair of CMOS transistors, the other of which may include the same configuration or a different configuration. A method for fabricating the hybrid transistor structure includes forming a gate structure surrounding a suspended portion (52) of an upper patterned semiconductor layer (53) and extending down to a surface of a lower semiconductor layer (42).
    Type: Application
    Filed: May 8, 2006
    Publication date: November 8, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Zhonghai Shi, Voon-Yew Thean, Ted White
  • Publication number: 20070241403
    Abstract: A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.
    Type: Application
    Filed: April 12, 2006
    Publication date: October 18, 2007
    Inventors: Voon-Yew Thean, Bich-Yen Nguyen, Mariam Sadaka, Victor Vartanian, Ted White
  • Publication number: 20070238233
    Abstract: A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 11, 2007
    Inventors: Mariam Sadaka, Bich-Yen Nguyen, Ted White
  • Publication number: 20070238250
    Abstract: A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 11, 2007
    Inventors: Da Zhang, Ted White, Bich-Yen Nguyen
  • Publication number: 20070235807
    Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
    Type: Application
    Filed: May 1, 2007
    Publication date: October 11, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Ted White, Alexander Barr, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka, Voon-Yew Thean
  • Publication number: 20070210314
    Abstract: A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.
    Type: Application
    Filed: March 10, 2006
    Publication date: September 13, 2007
    Inventors: Brian Winstead, Ted White, Da Zhang
  • Publication number: 20070190745
    Abstract: A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.
    Type: Application
    Filed: February 10, 2006
    Publication date: August 16, 2007
    Inventors: Mariam Sadaka, Bich-Yen Nguyen, Voon-Yew Thean, Ted White
  • Publication number: 20070134891
    Abstract: A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 14, 2007
    Inventors: Olubunmi Adetutu, Robert Jones, Ted White
  • Publication number: 20070108481
    Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Brian Goolsby, Linda McCormick, Bich-Yen Nguyen, Colita Parker, Mariam Sadaka, Victor Vartanian, Ted White, Melissa Zavala
  • Publication number: 20070082453
    Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 12, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Marius Orlowski, Alexander Barr, Mariam Sadaka, Ted White
  • Publication number: 20070048919
    Abstract: A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
    Type: Application
    Filed: August 23, 2005
    Publication date: March 1, 2007
    Inventors: Olubunmi Adetutu, Mariam Sadaka, Ted White, Bich-Yen Nguyen
  • Publication number: 20060228842
    Abstract: A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.
    Type: Application
    Filed: April 7, 2005
    Publication date: October 12, 2006
    Inventors: Da Zhang, Jing Liu, Bich-Yen Nguyen, Voon-Yew Thean, Ted White
  • Publication number: 20060228872
    Abstract: A method of forming a semiconductor device includes forming a local strain-inducing structure of a first semiconductor material at a point location within a dielectric layer. The local strain-inducing structure has a prescribed geometry with a surface disposed above a surface of the dielectric layer. A second semiconductor material is formed over the dielectric layer and the local strain inducing structure, wherein formation of a first portion of the second material over the dielectric layer provides a poly crystalline structure of the second material and wherein formation of a second portion of the second material over the local strain-inducing structure provides a single crystalline structure of the second material subject to mechanical strain by the surface of the local strain-inducing structure. The single crystalline structure serves as a strained semiconductor layer of the semiconductor device.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 12, 2006
    Inventors: Bich-Yen Nguyen, Shawn Thomas, Lubomir Cergel, Mariam Sadaka, Voon-Yew Thean, Peter Wennekers, Ted White, Andreas Wild, Detlev Gruetzmacher, Oliver Schmidt
  • Publication number: 20060226492
    Abstract: A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. In addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 12, 2006
    Inventors: Bich-Yen Nguyen, Shawn Thomas, Lubomir Cergel, Mariam Sadaka, Voon-Yew Thean, Peter Wennekers, Ted White, Andreas Wild, Detlev Gruetzmacher, Oliver Schmidt
  • Publication number: 20060228851
    Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 12, 2006
    Inventors: Mariam Sadaka, Alexander Barr, Dejan Jovanovic, Bich-Yen Nguyen, Voon-Yew Thean, Shawn Thomas, Ted White
  • Publication number: 20060094169
    Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Ted White, Alexander Barr, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka, Voon-Yew Thean
  • Publication number: 20060084235
    Abstract: A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.
    Type: Application
    Filed: October 15, 2004
    Publication date: April 20, 2006
    Inventors: Alexander Barr, Olubunmi Adetutu, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka, Voon-Yew Thean, Ted White
  • Patent number: D629391
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: December 21, 2010
    Assignee: Audyssey Laboratories, Inc.
    Inventors: Michael Solomon, Chris Kyriakakis, Andrew Dow Turner, Alex Rasmussen, Ted White, Brad Babineaux, Merrick Mosst, Tyson Osborne Yaberg