Abstract: Clock driving circuitry for a high speed interline transfer CCD imager generates complementary voltage waveforms, each of which shifts from a respective first voltage level to a respective second voltage level once for every line in a frame to empty each of the imager's vertical shift registers in succession and to a respective third voltage level once each frame to charge all of the photodiodes of the imager. In generating one of the complementary waveforms, a positive third voltage level is superimposed upon the waveform through at least one isolation device and a separate switch is provided to discharge the waveform back to the second voltage level. In generating the other of the complementary waveforms, the waveform is switched from the second voltage level to a negative third voltage level and then switched back from the negative third voltage level to the second voltage level.

Abstract: A solid-state image sensor includes a substrate of a semiconductor material of one conductivity type having a surface. A plurality of spaced, parallel CCDs are in the substrate at the surface. Each CCD includes a channel region of the opposite conductivity type in the substrate and a plurality of conductive gates extending across and insulated from the channel region. The conductive gates extend laterally across the channel regions of all of the CCDs and divide the channel regions into a plurality of phases and pixels. A drain region of the opposite conductivity type is in the substrate at the surface and extends along the channel region of at least one of the CCDs. A separate overflow channel region of the opposite conductivity type is in the substrate at said surface and extends from each of the CCD channel region phases to the adjacent drain region.

Abstract: In a CCD in which a pixel is defined by at least two adjacent gate electrodes, voltages are applied to both gate electrodes to simultaneously place both gates of each pixel in a mode of operation whereby holes are accumulated at the surface of a substrate in which the CCD is formed. Preferably one of these voltages is at a higher potential level than the other.

Abstract: An interline transfer type area image sensor is described which can selectively operate in either an interlaced or non-interlaced read-out mode. The sensor includes a plurality of vertical CCD shift registers. Each shift register has an ion implanted shift transfer barrier or storage regions such that only one layer of gate electrode is required by each voltage clock, and a structure for selectively applying voltages to the clock lines for alternate rows of one or both of the vertical shift register electrodes.

Abstract: A CCD imager includes a substrate of a semiconductor material having a plurality of photodetectors therein at a top surface thereof and arranged either in a line or in an array of rows and columns. A CCD shift register is in the substrate along but spaced from one side of the line or each column of photodetectors. Between each photodetector and its adjacent shift register is an accumulation region. A transfer gate is provided between the shift register and its adjacent line or column of accumulation regions. A transfer gate is provided between each line or row of photodetectors and the adjacent accumulation regions. A first anti-blooming drain region is provided along each line or column of photodetectors on the side of the photodetectors opposite the accumulation regions. A separate second anti-blooming drain is provided along a side of each accumulation region in the area of the substrate between the shift register and the photodetectors.

Abstract: In accordance with the present invention, a conventional area image sensor of the interline transfer type is so configured as to be readable in blocks of adjacent photosite rows, thereby enabling the modified sensor to be read out at fast frame rates. The resulting sensor, although designed for block readout, can be produced using conventional manufacturing processes.

Abstract: An area image sensor comprised of an array of photosites arranged in rows and columns is disclosed. The sensor is readable in blocks of adjacent photosite rows, thereby to enable operation of the sensor at frame rates on the order of thousands of frames per second.

Abstract: Fixed pattern noise manifested as percentage variations between the apparent sensitivities of sensor elements in a solid state image sensing array is reduced by removing one or more percentage portions of charge from a charge packet generated by an element of the sensing array. In a preferred embodiment, a percentage portion of charge is removed by dumping the portion of charge appearing under one part of a split electrode in a charge coupled device (CCD) shift register. A programmed memory controls the operation of the split electrode CCD device to provide the required corrections. To program the memory, the output of the image sensing array is measured with a non-image-wise input; and a particular charge packet size (e.g. the smallest useable charge packet produced by the array) is chosen as a reference.

Abstract: A color line sensor for use in color film scanning apparatus is disclosed. The scanning apparatus is of the type employing a line sensor for scanning an image of the film in one direction and having means for continuously displacing the image relative to the sensor, in a direction generally perpendicular to the line scan direction, to effect a raster scan composed of a number of equally spaced lines. The color line sensor includes a plurality of line sensing arrays, spaced apart from each other by a distance corresponding to the spacing between scan lines in the raster. Each line sensing array is sensitized to a particular color of light so that a plurality of color signals are produced by the sensor. Respective color signals from the line sensing arrays are delayed by an amount sufficient to cause all the color signals emerging from the color line sensor at any given instant to represent the same point in the image.

Abstract: A multiple, superposed-channel, solid-state, color image sensor of the "parallel transfer" type includes a plurality of superposed generally "ladder shaped" channels in a semiconductor substrate. One "side rail" of the ladder shape provides the channel structure for a multiple, superposed-channel signal handling device, such as a charge coupled shift register. The "rungs" of the ladder shape provide a plurality of multiple, superposed-channel color image sensing sites, and the other "side rail" of the ladder shape provides a plurality of superposed "anti-bloom" drains, one drain per channel. Electrical contact to a buried channel is provided by a V-groove etching technique. A V-groove extending from the surface of the device into the buried channel provides physical access to the buried channel. A conductor, in ohmic contact with the channel, extends from the bottom of the V-groove to the surface of the device to provide electrical contact with the buried channel.

Abstract: A solid state image sensing device comprises an array of picture sensing elements which are MOS transistors formed on a bulk of semiconductor material. The transistors are of a V-MOS configuration and have respective sources, V-shaped gates, and drains. The source-to-bulk diode of a V-MOS picture sensing element functions as a photodiode and is disposed near the surface of the array to receive a respective portion of imagewise illumination. In a preferred embodiment, the drain of the V-MOS picture sensing element is buried in the bulk directly beneath its respective source. The source, in conjunction with its gate, acts as a multiplex switch for the photodiode.