Abstract: This application discloses a virtual character display method performed by a computer device and relates to the field of application programs supporting virtual worlds. The method includes: displaying a virtual world, the virtual world including at least two scene block buildings, and each of the scene block buildings being configured for displaying virtual characters in activity statuses of a same type; determining a first social status posted by a user of the computer device associated with a first user account of the virtual world; and displaying a first virtual character corresponding to the first user account in a first scene block building corresponding to the first social status, the first virtual character being in an activity status corresponding to the first social status and having a scene element matching the activity status corresponding to the first scene block building.

Abstract: This application discloses a friend-making content recommendation method and apparatus, a device, and a storage medium, and relates to the field of friend-making content recommendation technologies.

Abstract: A shift register includes a first input sub-circuit configured to cause a first power supply voltage to be written into a first node, a second input sub-circuit configured to cause a signal of the first-type clock signal end to be written into the first node, a first output unit configured to cause a second power supply voltage to be written into a signal output end, a first control sub-circuit configured to cause a signal of a second-type clock signal end to be written into a second node, a second control sub-circuit configured to cause the signal of the second-type clock signal end to be written into a third node, a third control sub-circuit configured to cause conduction between the third node and the second node, and a second output unit configured to cause the first power supply voltage to be written into the signal output end.

Abstract: The present disclosure provides a shift register, a driving method thereof, a display substrate and a display device. The shift register includes a storage sub-circuit, a node control sub-circuit and an output control sub-circuit, wherein the storage sub-circuit, electrically connected to a first node and a first power supply terminal respectively, is configured to store a voltage difference between a signal of the first node and a signal of the first power supply terminal; the node control sub-circuit, electrically connected to a signal input terminal, a first clock signal terminal, a second clock signal terminal, the first node and a second node respectively, is configured to provide a signal of the signal input terminal to the first node under the control of the first clock signal terminal and provide the signal of the first node to the second node under the control of the second clock signal terminal.

Abstract: A display substrate includes an underlay substrate, and a first semiconductor layer, first conductive layer, second semiconductor layer, second conductive layer, and third conductive layer which are arranged on the underlay substrate. The first semiconductor layer includes an active layer of at least one transistor of a second semiconductor type of a shift register unit. The first conductive layer includes a control electrode of the at least one transistor of the second semiconductor type and a first electrode of at least one capacitor of the shift register unit. The second semiconductor layer includes an active layer of at least one transistor of a first semiconductor type of the shift register unit. The second conductive layer includes a control electrode of the at least one transistor of the first semiconductor type and a second electrode of the at least one capacitor of the shift register unit.

Abstract: A servo control method for a multi-joint hydraulic manipulator based on adaptive sliding mode is provided. A motion trajectory of an end of the multi-joint hydraulic manipulator in a workspace is generated, and expected angular displacement, angular velocity and angular acceleration of individual joints are calculated. An actual angular displacement and an actual angular velocity of the individual joints under a current position-pose are calculated. Combined with a dynamic model of the manipulator, a driving force of individual joints is calculated. Based on the expected angular displacement, the actual angular displacement and the driving force, a sliding-mode surface is constructed. The adaptive law is updated to perform adaptive sliding-mode control for the manipulator. A system for implementing the servo control method is also provided.

Abstract: Embodiments of this disclosure disclose an image data processing method and apparatus. The processing method includes: processing a first image and a second image by using a first neural network to obtain a homography matrix; determining a mapped image feature of a first image feature based on the homography matrix; fusing the mapped image feature and a second image feature to obtain a fused image feature; and processing the fused image feature by using a second neural network to obtain a first pixel height-to-depth ratio of the second image. In the embodiments of this disclosure, a dense and accurate pixel height-to-depth ratio can be obtained, thereby facilitating 3D scene modeling.

Abstract: A pixel circuit and a driving method therefor, a display panel, and a display device are provided. In the pixel circuit, a control terminal of the driving circuit is connected with the storage circuit at a first node, and the first light emission control circuit is connected with the first terminal of the driving circuit at a second node. The method includes: before a data writing phase, the first reset circuit turning on to reset the first node, and the first light emission control circuit turning on to reset the second node; during the data writing phase, the data writing circuit turning on, so as to write the data signal into the first terminal of the driving circuit; and during a light emitting phase, the first light emission control circuit turning on, and the light emitting element emitting light according to the drive current.

Abstract: A memory includes a memory cell array and a peripheral circuit, the peripheral circuit comprising at least a trigger circuit comprising a reference signal output circuit and a fail bit signal output circuit, wherein the fail bit signal output circuit is configured to generate a fail bit signal according to a test signal obtained from verification of the memory, and the reference signal output circuit is configured to output a plurality of reference signals; and a comparator coupled with the trigger circuit and configured to compare the fail bit signal with the at least one reference signal to output a verification result.

Abstract: Disclosed in embodiments of the present disclosure are a method and an apparatus for generating a spatial geometric information estimation model, a computer-readable storage medium, and an electronic device. The method includes: acquiring point cloud data collected for a preset scene and a scene image captured for the preset scene; determining coordinates corresponding to the point cloud data in a camera coordinate system corresponding to the scene image; determining, based on the coordinates, annotation spatial geometric information of a target pixel in the scene image corresponding to the point cloud data; and training an initial model by using the scene image as an input of a preset initial model and the annotation spatial geometric information of the target pixel as an expected output of the initial model, to obtain a spatial geometric information estimation model.

Abstract: According to some aspects, a memory includes a bit line discharge circuit and a bit line coupled to the bit line discharge circuit. The bit line discharge circuit includes a transistor, a control branch, and a first discharge branch. A gate of the transistor is connected with the control branch. One of a source or a drain of the transistor is connected with the first discharge branch. Another of the source or the drain of the transistor is connected with the bit line. The control branch is configured to turn on the transistor. The first discharge branch is configured to discharge the bit line at a set discharge speed when the transistor is turned on.

Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate, a transistor structure and a shielding structure, wherein the transistor structure and the shielding structure both arranged on the base substrate, the shielding structure including a first shielding part, at least part of the first shielding part extending in a direction perpendicular to the base substrate, and an orthographic projection of the first shielding part onto the base substrate being located at a periphery of an orthographic projection of a channel part of the corresponding transistor structure on the base substrate.

Abstract: Disclosed is a display panel, including a light shielding layer and at least two pixel circuits. Each pixel circuit includes at least two types of transistors for receiving different signals. The light shielding layer includes a first light shielding structure and a second light shielding structure. Orthographic projections of the first and second light shielding structures on the driving circuit layer overlap with the active portions of different types of transistors, adjacent first light shielding structures are connected together, and/or adjacent second light shielding structures are connected together, which may increase the static discharge area and path of the light shielding layer, so that static electricity accumulated in the process may be released in a timely manner or evenly distributed, to prevent static electricity from damaging the shading layer or other film layers, and achieve a good display effect. Also disclosed is a display device including the display panel.

Abstract: An electric drive module and an electric drive equipment are provided, the electric drive module comprises a housing, a force output assembly, a flexible gear, a rotor, a stator, a wave generator, and a cooling pipe, the stator is configured to drive the rotor to rotate relative to the housing, when the rotor rotates, the wave generator drives the flexible gear to deform to drive the rigid gear to rotate, at least part of the cooling pipe is received in and closes to the stator. The electric drive module is compact and space saving, the flexible gear is secured to the housing, the rotation of the rigid gear driven by the deformation of the flexible outputs power, which is low rotational inertia and decreases vibration, the cooling pipe arranged in the stator can directly dissipate heat from the stator with high heat dissipation efficiency.

Abstract: A memory device includes: a memory cell array including a memory plane, wherein the memory plane includes a plurality of memory sub-planes; and a peripheral circuit coupled with the memory cell array and configured to: perform verify operations on the plurality of memory sub-planes at the same time, to obtain a verify result for the memory plane; and determine the number of fail bits of the memory plane based on the verify result.

Abstract: In an information transmission method, a display interface of a virtual scene is displayed. The virtual scene includes a first virtual character. The first virtual character corresponds to a first user account. A second virtual character is controlled to move toward the first virtual character in the virtual scene to send first information to the first virtual character. The second virtual character corresponds to a second user account. Based on the second virtual character entering a first region in which the first virtual character is located, a first action animation of the second virtual character sending the first information to the first virtual character is displayed, and preview information of the first information is displayed.

Abstract: Examples of the present disclosure provide memories, operation methods thereof, and memory systems. A first discharge circuit in an example memory is able to discharge a bit line through a first discharge transistor based on a first voltage received. A second discharge circuit is able to discharge a source line through a second discharge transistor based on a second voltage received. The second voltage is higher than the first voltage, and a discharge current outputted by the second discharge transistor is greater than a discharge current outputted by the first discharge transistor.

Abstract: Implementations of the present disclosure disclose a memory device, an operation method thereof and a memory system. The memory device includes a peripheral circuit. The peripheral circuit includes a set of page buffers, an error bit signal generating circuit and a plurality of first transistors, wherein the set of page buffers includes N page buffers with N being an integer larger than 1, the error bit signal generating circuit is connected with the sensing nodes of the page buffers, and the respective sensing nodes of every two adjacent page buffers in the set of page buffers are connected with one of the first transistors.

Abstract: A verify failbit count (VFC) circuit includes a counter including a plurality of counter stages coupled one after another and including one or more cache stages in a cache group and a plurality of reception stages divided into a plurality of reception groups each including one or more reception stages of the plurality of reception stages. Each of the reception stages is configured to receive one of a plurality of verification bits generated by a verification operation of a memory device. The counter further includes one or more switches each coupled between two neighboring ones of the plurality of reception groups.

Abstract: A verify fail bit count (VFC) circuit includes a power-supply transistor, a sense stage coupled to the power-supply transistor and configured to, in response to a verification operation, sense each of a plurality of verification bits being a fail bit or a pass bit, a plurality of storage stages coupled to the sense stage in parallel and each configured to store one fail bit sensed by the sense stage based on a sequence from near to far from the sense stage, and a common ground transistor coupled to the sense stage and the plurality of storage stages.