Abstract: A memory includes a memory cell array and a peripheral circuit, the peripheral circuit comprising at least a trigger circuit comprising a reference signal output circuit and a fail bit signal output circuit, wherein the fail bit signal output circuit is configured to generate a fail bit signal according to a test signal obtained from verification of the memory, and the reference signal output circuit is configured to output a plurality of reference signals; and a comparator coupled with the trigger circuit and configured to compare the fail bit signal with the at least one reference signal to output a verification result.

Abstract: Disclosed in embodiments of the present disclosure are a method and an apparatus for generating a spatial geometric information estimation model, a computer-readable storage medium, and an electronic device. The method includes: acquiring point cloud data collected for a preset scene and a scene image captured for the preset scene; determining coordinates corresponding to the point cloud data in a camera coordinate system corresponding to the scene image; determining, based on the coordinates, annotation spatial geometric information of a target pixel in the scene image corresponding to the point cloud data; and training an initial model by using the scene image as an input of a preset initial model and the annotation spatial geometric information of the target pixel as an expected output of the initial model, to obtain a spatial geometric information estimation model.

Abstract: According to some aspects, a memory includes a bit line discharge circuit and a bit line coupled to the bit line discharge circuit. The bit line discharge circuit includes a transistor, a control branch, and a first discharge branch. A gate of the transistor is connected with the control branch. One of a source or a drain of the transistor is connected with the first discharge branch. Another of the source or the drain of the transistor is connected with the bit line. The control branch is configured to turn on the transistor. The first discharge branch is configured to discharge the bit line at a set discharge speed when the transistor is turned on.

Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate, a transistor structure and a shielding structure, wherein the transistor structure and the shielding structure both arranged on the base substrate, the shielding structure including a first shielding part, at least part of the first shielding part extending in a direction perpendicular to the base substrate, and an orthographic projection of the first shielding part onto the base substrate being located at a periphery of an orthographic projection of a channel part of the corresponding transistor structure on the base substrate.

Abstract: Disclosed is a display panel, including a light shielding layer and at least two pixel circuits. Each pixel circuit includes at least two types of transistors for receiving different signals. The light shielding layer includes a first light shielding structure and a second light shielding structure. Orthographic projections of the first and second light shielding structures on the driving circuit layer overlap with the active portions of different types of transistors, adjacent first light shielding structures are connected together, and/or adjacent second light shielding structures are connected together, which may increase the static discharge area and path of the light shielding layer, so that static electricity accumulated in the process may be released in a timely manner or evenly distributed, to prevent static electricity from damaging the shading layer or other film layers, and achieve a good display effect. Also disclosed is a display device including the display panel.

Abstract: An electric drive module and an electric drive equipment are provided, the electric drive module comprises a housing, a force output assembly, a flexible gear, a rotor, a stator, a wave generator, and a cooling pipe, the stator is configured to drive the rotor to rotate relative to the housing, when the rotor rotates, the wave generator drives the flexible gear to deform to drive the rigid gear to rotate, at least part of the cooling pipe is received in and closes to the stator. The electric drive module is compact and space saving, the flexible gear is secured to the housing, the rotation of the rigid gear driven by the deformation of the flexible outputs power, which is low rotational inertia and decreases vibration, the cooling pipe arranged in the stator can directly dissipate heat from the stator with high heat dissipation efficiency.

Abstract: A memory device includes: a memory cell array including a memory plane, wherein the memory plane includes a plurality of memory sub-planes; and a peripheral circuit coupled with the memory cell array and configured to: perform verify operations on the plurality of memory sub-planes at the same time, to obtain a verify result for the memory plane; and determine the number of fail bits of the memory plane based on the verify result.

Abstract: In an information transmission method, a display interface of a virtual scene is displayed. The virtual scene includes a first virtual character. The first virtual character corresponds to a first user account. A second virtual character is controlled to move toward the first virtual character in the virtual scene to send first information to the first virtual character. The second virtual character corresponds to a second user account. Based on the second virtual character entering a first region in which the first virtual character is located, a first action animation of the second virtual character sending the first information to the first virtual character is displayed, and preview information of the first information is displayed.

Abstract: Examples of the present disclosure provide memories, operation methods thereof, and memory systems. A first discharge circuit in an example memory is able to discharge a bit line through a first discharge transistor based on a first voltage received. A second discharge circuit is able to discharge a source line through a second discharge transistor based on a second voltage received. The second voltage is higher than the first voltage, and a discharge current outputted by the second discharge transistor is greater than a discharge current outputted by the first discharge transistor.

Abstract: Implementations of the present disclosure disclose a memory device, an operation method thereof and a memory system. The memory device includes a peripheral circuit. The peripheral circuit includes a set of page buffers, an error bit signal generating circuit and a plurality of first transistors, wherein the set of page buffers includes N page buffers with N being an integer larger than 1, the error bit signal generating circuit is connected with the sensing nodes of the page buffers, and the respective sensing nodes of every two adjacent page buffers in the set of page buffers are connected with one of the first transistors.

Abstract: A verify failbit count (VFC) circuit includes a counter including a plurality of counter stages coupled one after another and including one or more cache stages in a cache group and a plurality of reception stages divided into a plurality of reception groups each including one or more reception stages of the plurality of reception stages. Each of the reception stages is configured to receive one of a plurality of verification bits generated by a verification operation of a memory device. The counter further includes one or more switches each coupled between two neighboring ones of the plurality of reception groups.

Abstract: A verify fail bit count (VFC) circuit includes a power-supply transistor, a sense stage coupled to the power-supply transistor and configured to, in response to a verification operation, sense each of a plurality of verification bits being a fail bit or a pass bit, a plurality of storage stages coupled to the sense stage in parallel and each configured to store one fail bit sensed by the sense stage based on a sequence from near to far from the sense stage, and a common ground transistor coupled to the sense stage and the plurality of storage stages.

Abstract: A rehabilitation training system. The A rehabilitation training equipment includes a driving device, a back placement device, a leg aid device, a cushion device, a first feedback device, and a control device. The driving device is configured to adjust rotation angles between the back placement device, the cushion device, and the leg aid device to achieve a posture training mode selected from a plurality of posture training modes including a standing mode, a sitting-up mode, and a lying mode. The first feedback device is used to obtain core muscle strength parameters of the human body. The control device is electrically connected to the first feedback device and the driving device, and is configured to obtain the core muscle strength parameters and send a control signal to the driving device.

Abstract: In a method for displaying a location of a first virtual character, the first virtual character located in a first virtual scene is displayed. Based on a first operation on the first virtual character, a first interface element corresponding to the first virtual character is displayed. The first interface element is configured to indicate a location of the first virtual character. Based on a second operation on the first interface element and the location of the first virtual character changing from the first virtual scene to a second virtual scene, the second virtual scene in which the first virtual character is located is displayed, and the first virtual character in the second virtual scene is displayed. Apparatus and non-transitory computer-readable storage medium counterpart embodiments are also contemplated.

Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a stretchable area, the stretchable area comprises multiple pixel island areas spaced apart from each other, multiple hole areas, and connection bridge areas located between the pixel island areas and the hole areas; each of the hole areas is provided with one or more openings, and comprises a composite structural layer stacked on the substrate, each of the openings penetrates through the composite structural layer and a part of the opening is provided in the substrate, the opening penetrates through or does not penetrate through the substrate, and the wall of the opening is provided with separation grooves; and each of the hole areas further comprises a functional film layer provided on the composite structural layer and on the wall of each opening, and the functional film layer is separated at the separation grooves.

Abstract: Disclosed is a drive control circuit including an input circuit (10), a first output circuit (11), and a second output circuit (12). The first output circuit (11) is electrically connected with the input circuit (10) and a first output end (OUT1) and is configured to output a first output signal from the first output end (OUT1) under control of the input circuit (11). The second output circuit (12) is electrically connected with the input circuit (10) and a second output end (OUT2), or electrically connected with the first output end (OUT1) and a second output end (OUT2), and is configured to output a second output signal from the second output end (OUT2) under control of the input circuit (10) or the first output end (OUT1). The first output signal is different from the second output signal.

Abstract: The present disclosure provides a memory device and an operation method thereof, and a memory system, wherein the memory device includes a memory array and a page buffer circuit coupled with a bit line in the memory array; the page buffer circuit includes a first charge circuit and a second charge circuit coupled to a first sensing node along with the first charge circuit; and the operation method of the memory device includes: in a first charge stage, charging the first sensing node to a first voltage through the first charge circuit; and in a second charge stage, charging the first sensing node and the bit line to a second voltage through the second charge circuit, wherein the second voltage is higher than the first voltage.

Abstract: Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bit line and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bit line can include a first bit line segment coupled to the first memory string group and a second bit line segment coupled to the second memory string group. The buffer can be coupled to the memory array by the bit line. The memory array and the buffer can be included in separate first and second dies, respectively, and the first die can be bonded to the second die.

Abstract: Embodiments of this application provide a virtual social scene display method performed by a terminal. The method includes: displaying a virtual social scene in which a plurality of virtual objects corresponding to different social accounts perform social interactions; displaying a permission setting control in a chat interface when at least two virtual objects belong to a same chat group and the chat group is in a public state, a distance between the virtual objects in the chat group being less than a distance threshold; and setting the chat group to a private chat state in response to a trigger operation on the permission setting control. According to the solution provided in the embodiments of this application, chat group setting in the virtual social scene is optimized, and social types in the virtual social scene are enriched.