Patents by Inventor Teng-Yuan Lo
Teng-Yuan Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047408Abstract: An embodiment semiconductor device may include an electrical interconnect layer, a bonding pad electrically coupled to the electrical interconnect layer, a stacked film structure including a first film partially covering a surface of the bonding pad and a second film partially covering the first film, a first aperture formed in the first film over a portion of the surface of the bonding pad, a second aperture formed in the second film such that the second aperture is larger than the first aperture and is formed over the first aperture such that the first aperture is located entirely below an area of the second aperture, and a solder material portion formed in contact with the bonding pad. The solder material portion may include a first width that is less than a size of the second aperture such that the solder material portion does not contact the second film.Type: ApplicationFiled: August 8, 2022Publication date: February 8, 2024Inventors: Amram Eitan, Wen-Yi Lin, Teng-Yuan Lo
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Publication number: 20230253300Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.Type: ApplicationFiled: March 28, 2023Publication date: August 10, 2023Inventors: Kuo Lung Pan, Yu-Chia Lai, Teng-Yuan Lo, Mao-Yen Chang, Po-Yuan Teng, Chen-Hua YU, Chung-Shi Liu, Hao-Yi Tsai, Ting-Hao Kuo
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Patent number: 11646255Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.Type: GrantFiled: March 18, 2021Date of Patent: May 9, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu, Po-Yuan Teng, Teng-Yuan Lo, Mao-Yen Chang
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Publication number: 20230090895Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.Type: ApplicationFiled: November 21, 2022Publication date: March 23, 2023Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
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Publication number: 20230066968Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Ming-Hung Tseng, Yen-Liang Lin, Ban-Li Wu, Hsiu-Jen Lin, Teng-Yuan Lo, Hao-Yi Tsai
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Patent number: 11508671Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.Type: GrantFiled: September 9, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
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Patent number: 11508656Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.Type: GrantFiled: June 28, 2021Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
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Publication number: 20220367301Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Teng-Yuan Lo, Lipu Kris Chuang, Hsin-Yu Pan
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Publication number: 20220302003Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Inventors: Kuo Lung PAN, Yu-Chia LAI, Tin-Hao KUO, Hao-Yi TSAI, Chung-Shi LIU, Chen-Hua YU, Po-Yuan TENG, Teng-Yuan LO, Mao-Yen CHANG
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Patent number: 11450581Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.Type: GrantFiled: January 29, 2021Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Yuan Lo, Lipu Kris Chuang, Hsin-Yu Pan
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Publication number: 20220068736Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.Type: ApplicationFiled: January 29, 2021Publication date: March 3, 2022Inventors: Teng-Yuan Lo, Lipu Kris Chuang, Hsin-Yu Pan
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Publication number: 20210327806Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 11049805Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.Type: GrantFiled: February 4, 2019Date of Patent: June 29, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 10985115Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.Type: GrantFiled: June 19, 2020Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
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Publication number: 20200402927Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.Type: ApplicationFiled: September 9, 2020Publication date: December 24, 2020Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
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Publication number: 20200321290Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
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Patent number: 10797008Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided.Type: GrantFiled: November 21, 2019Date of Patent: October 6, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
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Patent number: 10734328Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.Type: GrantFiled: December 16, 2019Date of Patent: August 4, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
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Publication number: 20200118945Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
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Publication number: 20200091091Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided.Type: ApplicationFiled: November 21, 2019Publication date: March 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang