Abstract: An analog signal photo-electrically converted in a pixel of a light receiving area is converted to a digital signal by an ADC. The digital signal is processed by a digital signal processing circuit, and then, successively output as a digital video signal. The digital signal processing circuit has a first signal processing block for detecting and correcting a pixel defect and preventing a noise, and a second signal processing block for restoring apparent resolution lost by the processing by the first signal processing block.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0–11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.