Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first nanosheet layer. The first nanosheet layer includes a first channel region, and a heavily doped epitaxial region of a first type. Further, the semiconductor structure includes a second nanosheet layer. The second nanosheet layer includes a second channel region, a heavily doped epitaxial region of a second type disposed above the first nanosheet layer, and a first gate surrounding the first channel region and the second channel region. Additionally, the semiconductor structure includes a protection diode. The protection diode includes a source, a drain, and a second gate. The drain is connected to the first gate, and the second gate is connected to the source.

Abstract: A semiconductor structure includes a semiconductor device that includes a diode structure including: stacked nanolayers including alternating Si nanolayers and SiGe nanolayers; a p-type doped anode region in direct contact with the stacked nanolayers; and an n-type doped cathode region in direct contact with the stacked nanolayers; and a plurality of field effect transistor (FET) structures. Each FET structure comprises Si nanolayers that are coplanar with the Si nanolayers of the diode structure. The structure can be employed, at least in part, to realize a bandgap reference circuit.

Abstract: A method includes obtaining a plurality of macro cells, wherein each macro cell comprises a corresponding plurality of transistors and determining whether each of the plurality of macro cells is compliant with a set of one or more design rules associated with one or more backside wiring layers. The method includes providing, based on a result of the determining, one or more conductive shunt paths for at least one of the macro cells, where each transistor in each macro cell comprises a respective conductive shunt path between a gate structure and a source/drain region of the corresponding transistor.

Abstract: A semiconductor structure comprises at least one bias structure comprising a first diffusion region having a designated doping type, and at least one protection diode comprising a second diffusion region having the designated doping type, wherein the at least one bias structure is connected to the at least one protection diode through at least one contact line.

Abstract: A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) formed on a substrate and connected to a backside metal line of a backside power distribution network (BSPDN). The semiconductor device also includes a lateral junction diode co-integrated with the stacked nanosheet FET.

Abstract: A microelectronic structure includes a nanosheet transistor device stack having a first transistor device stacked on a second transistor device. The first transistor device includes a source and drain. The second transistor device includes terminal connections. A gate is shared between the first transistor device and the second transistor device. The first transistor device is configured to conduct a current between the drain and the source based on a voltage on the gate. The terminal connections of the second transistor device are vestigial irrespective of a voltage applied to the gate, such that the second transistor device is always passive.

Abstract: Frontside transistor devices and a frontside passive device are incorporated in a “substrate-less” structure having backside contacts, power rails, and power distribution network. The passive device includes two heavily doped semiconductor regions bridged by a lowly doped semiconductor region. Diffusion breaks located on the frontside may laterally confine the passive device.

Abstract: Techniques are provided for multi-FET vertical stack modeling.

Abstract: Aspects of the disclosed invention provide a semiconductor structure for a semiconductor chip with two layers of semiconductor devices, where the first layer of semiconductor devices directly contacts a semiconductor substrate and connects to a first frontside interconnect wiring. The first layer of semiconductor devices includes at least one trench semiconductor device such as a deep trench capacitor. The first frontside interconnect wiring is electrically connected to the second frontside interconnect wiring by one or more joined metal plugs. The second layer of active devices connects to a backside power delivery network and the second frontside interconnect wiring. The semiconductor chip with two layers of semiconductor devices that are bonded together provides one layer of semiconductor devices capable of being in a portion of the semiconductor substrate and a second layer of semiconductor devices with a backside power delivery network.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first nanosheet layer. The first nanosheet layer includes a first channel region, and a heavily doped epitaxial region of a first type. Further, the semiconductor structure includes a second nanosheet layer. The second nanosheet layer includes a second channel region, a heavily doped epitaxial region of a second type disposed above the first nanosheet layer, and a first gate surrounding the first channel region and the second channel region. Additionally, the semiconductor structure includes a protection diode. The protection diode includes a source, a drain, and a second gate. The drain is connected to the first gate, and the second gate is connected to the source.

Abstract: The present disclosure describes an illustrative semiconductor IC device that includes an antenna diode that drains electrical charge build up created during backside BEOL network fabrication processes. The semiconductor IC device includes an active semiconductor IC device upon which the backside BEOL network is to be fabricated and a handler semiconductor device that includes a diode doped region. Charge build up that may occur during the fabrication of the backside BEOL network may be dissipated through the diode doped region. As such, parasitic charge build up that may damage the semiconductor IC device is limited, thereby increasing yield of, and thereby limiting semiconductor IC device failure.

Abstract: A microelectronic structure includes a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices. Each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor. A gate cut located between the first row of stacked nano devices and the second row stacked nano devices. An interconnect located within gate cut. The interconnect is connected to a source/drain of one of the lower stacked transistors and the interconnect includes a non-uniform backside surface.

Abstract: A semiconductor including a short channel device including a vertical FET (Field-Effect Transistor), and a long channel device comprising a second vertical FET integrated with the short channel device. The long channel device including a plurality of short channel devices.

Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Abstract: Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.

Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Abstract: A method for fabricating a semiconductor device including multiple pairs of threshold voltage (Vt) devices includes forming a stack on a base structure having a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices and a third region corresponding to a third pair of Vt devices. The stack includes a first dipole layer, a first sacrificial layer formed on the first dipole layer, a second sacrificial layer formed on the first sacrificial layer, and a third sacrificial layer formed on the second sacrificial layer. The method further includes forming a second dipole layer different from the first dipole layer.

Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Abstract: A semiconductor including a short channel device including a vertical FET (Field-Effect Transistor), and a long channel device comprising a second vertical FET integrated with the short channel device. The long channel device including a plurality of short channel devices.