Abstract: Logic gate designs (e.g., NAND, NOR, Inverter) for stacked VTFET designs are provided. In one aspect, a logic gate device is provided. The logic gate device includes: at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2); a power rail connected to a power contact of the logic gate device; and a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device.

Abstract: Methods and systems for checking a wafer-level design for compliance with a rule include determining whether each chip layout out of multiple chip layouts complies internally with one or more layout design rules. A tile area is determined, having a size that is based on the one or more layout design rules, that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined whether portions of the plurality of chip layouts inside the tile area comply with the one or more layout design rules. The chip layouts are modified, if chip layout area within the tile area fails to comply with the design rule, to bring non-compliant periphery chip regions into compliance.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: Semiconductor devices and methods of making the same include forming a stack of alternating layers of channel material and sacrificial material. The sacrificial material is etched away to free the layers of channel material. A gate stack is formed around the layers of channel material. At least one layer of channel material is deactivated. Source and drain regions are formed in contact with the at least one layer of active channel material.

Abstract: A vertical field-effect transistor (FET) device and an input/output (IO) FET device are formed. The vertical FET device is formed in a vertical FET device area of a substrate and the IO FET device is formed in an IO FET device area of the substrate. Forming the vertical FET device and the IO FET device includes forming a plurality of first fin structures in the vertical FET device area and forming at least two second fin structures in the IO FET device area. The at least two second fin structures are separated by a distance associated with a length of a channel connecting the at least two fin structures in the IO FET device area. The length of the channel is determined based on at least one voltage for implementing the IO FET device.

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

Abstract: A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A first vertical transistor device associated with a first conductivity type is formed within a first tier. A second vertical transistor device associated with a second conductivity type is formed within a second tier. The first vertical transistor device is connected to the second vertical transistor device to create a stacked vertical transistor device for three-dimensional monolithic integration such that the first vertical transistor device is located below the second vertical transistor device within the stacked vertical transistor device. Connecting the first vertical transistor device to the second vertical transistor device includes forming interconnects from a top of the second tier to respective positions within the first tier by forming vias and filling the vias with interconnect material.

Abstract: Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment, forming a first set of semiconductor fins vertically extending from a substrate, and forming a second set of semiconductor fins vertically extending from the substrate, the distance between the first set of fins and the second set of fins defines a length of a junction. Embodiments also include forming a first epitaxy layer on the substrate, and forming a second epitaxy layer atop a portion of the first epitaxy layer, wherein a PN junction is formed between the first epitaxy layer and the second epitaxy layer, wherein a length of the PN junction is defined by the first set of semiconductor fins and the second semiconductor fins. Embodiments include forming a first metal contact atop the first epitaxy layer, and forming a second metal contact atop the second epitaxy layer.

Abstract: Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment, forming a first set of semiconductor fins vertically extending from a substrate, and forming a second set of semiconductor fins vertically extending from the substrate, the distance between the first set of fins and the second set of fins defines a length of a junction. Embodiments also include forming a first epitaxy layer on the substrate, and forming a second epitaxy layer atop a portion of the first epitaxy layer, wherein a PN junction is formed between the first epitaxy layer and the second epitaxy layer, wherein a length of the PN junction is defined by the first set of semiconductor fins and the second semiconductor fins. Embodiments include forming a first metal contact atop the first epitaxy layer, and forming a second metal contact atop the second epitaxy layer.

Abstract: Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.

Abstract: Methods and systems for checking a wafer-level design for compliance with a rule include identifying nets that cross chip boundaries for each of a set of chip layouts. Interconnected identified nets are combined into one or more virtual ensembles having properties defined by a sum of properties of the respective interconnected nets. Chip layouts related to virtual ensembles that do not comply with a design rule are modified to bring non-compliant virtual ensembles into compliance.

Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer, patterning the heteroepitaxial film stack, forming a dummy gate stack with sidewall spacers, and forming a cladded or embedded epitaxial source/drain material along the patterned heteroepitaxial film stack sidewalls. The method further includes removing the dummy gate stack, partially removing the at least one sacrificial layer, and forming a replacement gate stack.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top surface of the substrate. At least one transistor contacts the bonding layer. The transistor includes at least one gate structure disposed on and in contact with a bottom surface of a semiconductor layer of the transistor. The semiconductor further includes a capacitor disposed adjacent to the transistor. The capacitor contacts the semiconductor layer of the transistor and extends down into the substrate. The method includes forming at least one transistor and then flipping the transistor. After the transistor has been flipped, the transistor is bonded to a new substrate. An initial substrate of the transistor is removed to expose a semiconductor layer. A capacitor is formed adjacent to the transistor and contacts with the semiconductor layer. A contact node is formed adjacent to the capacitor.

Abstract: A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second fin, the first fin arranged a first distance from the second fin, the first fin and the second fin extending from a first source/drain region through a channel region and into a second source/drain region on the substrate. The method further includes forming a third fin on the substrate, the third fin arranged in parallel with the first fin and between the first fin and the second fin, the third fin arranged a second distance from the first fin, the second distance is less than the first distance, the third fin having two distal ends arranged in the first source/drain region. A gate stack is formed over the first fin and the second fin.

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first source/drain layer, and a plurality of fins each disposed on and in contact with the first source/drain layer. Silicide regions are disposed within a portion of the first source/drain layer. A gate structure is in contact with the plurality of fins, and a second source/drain layer is disposed on the gate structure. The method includes forming silicide in a portion of a first source/drain layer. A first spacer layer is formed in contact with at least the silicide, the first source/drain layer and the plurality of fins. A gate structure is formed in contact with the plurality of fins and the first spacer layer. A second spacer layer is formed in contact with the gate structure and the plurality of fins.

Abstract: Methods and systems method for checking a semiconductor device for compliance with a rule include determining whether a fully depleted semiconductor on insulator (FDSOI) device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the FDSOI device. It is determined whether the FDSOI device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the FDSOI device. The chip layout is modified, if the FDSOI devices fails to comply with the first and second design rules, to bring the non-compliant FDSOI device into compliance.

Abstract: A method of forming a semiconductor circuit having FinFET devices that have fins of different height is provided. There is a shallow trench isolation layer (STI) on top of a semiconductor substrate. A first Fin Field Effect Transistor (FinFET) comprises a first semiconductor fin including a first layer that extends from a common substrate level through the STI layer to a first height above a top surface of the STI layer. There is a second FinFET comprising a second semiconductor fin including the first layer that extends from the common substrate level through the STI layer to the first height above the top surface of the STI layer, plus a second layer having a second height, plus a third layer having a third height. The second semiconductor fin is taller than the first semiconductor fin.