Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

Abstract: An apparatus and method for facilitating Atomic Force Microscopy, SEM Nano-Probing, Scanning Probe Microscopy, and Collimated Ion Milling, through the implementation of a removable, magnetized fixture for fixing the position of a sample requiring surface treatment, the fixture attachable to a holder requiring surface treatment, the holder being mountable in various instruments, the fixture being transportable in a container having a magnetized surface plate or disc for magnetic attachment of said fixture, with the container having a valve to permit alternative evacuation and backfill with an inert gas to protect the sample surface.

Abstract: Device structures that exhibit negative resistance characteristics and fabrication methods for such device structures. A signal is applied to a metal layer of a metal-insulator-semiconductor capacitor to cause a breakdown of an insulator layer of the metal-insulator-semiconductor capacitor at a location. The breakdown at the location of the insulator layer causes the metal-insulator-semiconductor capacitor to exhibit negative resistance. The metal layer may be comprised of a polycrystalline metal. A grain of the polycrystalline metal may penetrate through the insulator layer and into a portion of a substrate at the location of the breakdown.

Abstract: A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure is provided. The method may include measuring a capacitance-voltage (C-V) characteristic for the 3D field effect transistor device and identifying, based on the measured capacitance-voltage (C-V) characteristic, a Fin structure corresponding to the 3D field effect transistor device. The identified Fin structure is detached from the 3D field effect transistor device using a nanomanipulator probe tip. The detached Fin is then welded to the nanomanipulator probe tip using an incident focused ion beam having a voltage of less than about 1000 eV. The incident focused ion beam having a voltage of less than about 1000 eV is applied to a tip of the Fin that is welded to the nanomanipulator probe tip.

Abstract: A method of delayering a surface of a semiconductor structure may include applying a voltage in the range of about 50 eV to less than 300 eV to an inductively coupled Argon ion source operating at a radio frequency. A collimated ion beam incident on the surface of the semiconductor structure may be generated, from the Argon ion source, for the planar removal of layers of the surface. A structural material underlying the surface of the semiconductor structure is exposed using an end-point detector based on the planar removal of the layers.

Abstract: A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure is provided. The method may include measuring a capacitance-voltage (C-V) characteristic for the 3D field effect transistor device and identifying, based on the measured capacitance-voltage (C-V) characteristic, a Fin structure corresponding to the 3D field effect transistor device. The identified Fin structure is detached from the 3D field effect transistor device using a nanomanipulator probe tip. The detached Fin is then welded to the nanomanipulator probe tip using an incident focused ion beam having a voltage of less than about 1000 eV. The incident focused ion beam having a voltage of less than about 1000 eV is applied to a tip of the Fin that is welded to the nanomanipulator probe tip.

Abstract: A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure is provided. The method may include measuring a capacitance-voltage (C-V) characteristic for the 3D field effect transistor device and identifying, based on the measured capacitance-voltage (C-V) characteristic, a Fin structure corresponding to the 3D field effect transistor device. The identified Fin structure is detached from the 3D field effect transistor device using a nanomanipulator probe tip. The detached Fin is then welded to the nanomanipulator probe tip using an incident focused ion beam having a voltage of less than about 1000 eV. The incident focused ion beam having a voltage of less than about 1000 eV is applied to a tip of the Fin that is welded to the nanomanipulator probe tip. The tip of the Fin may then be sharpened by the focused ion beam.

Abstract: A method of generating a capacitance-voltage (C-V) characteristic for a discrete device formed within a semiconductor structure may include exposing first and second contact regions associated with the discrete device, coupling a high-frequency impedance probe having a frequency range of about 5 Mhz to about 110 Mhz to an impedance analyzer, and coupling the high-frequency impedance probe to a first and a second atomic force probe tip. Using an atomic force microscope, the first atomic force probe tip is coupled to the exposed first contact region and the second atomic force probe tip is coupled to the exposed second contact region. The C-V characteristic for the discrete device is then measured on the impedance analyzer, whereby the impedance analyzer applies an operating frequency corresponding to the frequency range of about 5 Mhz to about 110 Mhz to the first and second contact regions of the discrete device using the high-frequency impedance probe.

Abstract: A method of generating a capacitance-voltage (C-V) characteristic for a discrete device formed within a semiconductor structure may include exposing first and second contact regions associated with the discrete device, coupling a high-frequency impedance probe having a frequency range of about 5 Mhz to about 110 Mhz to an impedance analyzer, and coupling the high-frequency impedance probe to a first and a second atomic force probe tip. Using an atomic force microscope, the first atomic force probe tip is coupled to the exposed first contact region and the second atomic force probe tip is coupled to the exposed second contact region. The C-V characteristic for the discrete device is then measured on the impedance analyzer, whereby the impedance analyzer applies an operating frequency corresponding to the frequency range of about 5 Mhz to about 110 Mhz to the first and second contact regions of the discrete device using the high-frequency impedance probe.

Abstract: A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure is provided. The method may include measuring a capacitance-voltage (C-V) characteristic for the 3D field effect transistor device and identifying, based on the measured capacitance-voltage (C-V) characteristic, a Fin structure corresponding to the 3D field effect transistor device. The identified Fin structure is detached from the 3D field effect transistor device using a nanomanipulator probe tip. The detached Fin is then welded to the nanomanipulator probe tip using an incident focused ion beam having a voltage of less than about 1000 eV. The incident focused ion beam having a voltage of less than about 1000 eV is applied to a tip of the Fin that is welded to the nanomanipulator probe tip. The tip of the Fin may then be sharpened by the focused ion beam.

Abstract: A method of forming an integrated circuit structure includes forming a cap layer above a first ILD layer of a first metal level, the first ILD layer includes a recess filled with a first conductive material to form a first interconnect structure. Next, a second ILD layer is formed above the cap layer and a via is formed within the second ILD layer as a second interconnect structure of a second metal level. The via is aligned with the first interconnect structure. Subsequently, a portion of the cap layer is removed to extend the via to expose a top portion of the first conductive material then a passivation cap is selectively formed at a bottom portion of the via in the second ILD layer and the passivation cap contacting the top portion of the first conductive material. The passivation cap includes a metal alloy to form an interface between the bottom portion of the via and the first conductive material.

Abstract: A method of delayering a surface of a semiconductor structure may include applying a voltage in the range of about 50 eV to less than 300 eV to an inductively coupled Argon ion source operating at a radio frequency. A collimated ion beam incident on the surface of the semiconductor structure may be generated, from the Argon ion source, for the planar removal of layers of the surface. A structural material underlying the surface of the semiconductor structure is exposed using an end-point detector based on the planar removal of the layers.

Abstract: A method to form a voltage sensitive resistor (VSR) read only memory (ROM) device on a semiconductor substrate having a semiconductor device including depositing by chemical vapor deposition (CVD) a titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by at least an order of 102 when a predetermined voltage and current are applied to the VSR; and applying a predetermined voltage and current so as to make the CVD titanium nitride less resistive by at least an order of 102.

Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Abstract: Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 102, more preferably 103 and most preferably 104 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.