Patents by Inventor Terence L. Kane
Terence L. Kane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8367483Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Patent number: 8368069Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Patent number: 8367484Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Patent number: 8368070Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Method of fabricating a device using low temperature anneal processes, a device and design structure
Patent number: 8236709Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.Type: GrantFiled: July 29, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang -
METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE
Publication number: 20120180010Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.Type: ApplicationFiled: March 15, 2012Publication date: July 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony G. DOMENICUCCI, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang -
Publication number: 20120126367Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Publication number: 20120126366Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Publication number: 20120129340Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Publication number: 20120122280Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Patent number: 8125048Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: October 7, 2009Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Publication number: 20120001140Abstract: Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 102, more preferably 103 and most preferably 104 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Yun-Yu Wang, Keith Kwong Hon Wong
-
Patent number: 7993504Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: GrantFiled: February 7, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Terence L. Kane, Darrell L. Miles, John D. Sylvestri, Michael P. Tenney
-
Publication number: 20110079874Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: October 7, 2009Publication date: April 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
-
Method of Fabricating a Device Using Low Temperature Anneal Processes, a Device and Design Structure
Publication number: 20110027956Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony G. DOMENICUCCI, Terence L. KANE, Shreesh NARASIMHA, Karen A. NUMMY, Viorel ONTALUS, Yun-Yu WANG -
Patent number: 7881093Abstract: A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.Type: GrantFiled: August 4, 2008Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Terence L. Kane, Michael Tenney, Yun-Yu Wang
-
Publication number: 20100025819Abstract: A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.Type: ApplicationFiled: August 4, 2008Publication date: February 4, 2010Applicant: International Business Machines CorporationInventors: Anthony G. Domenicucci, Terence L. Kane, Michael Tenney, Yun-Yu Wang
-
Publication number: 20080128086Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: ApplicationFiled: February 7, 2008Publication date: June 5, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Darrell L. Miles, John D. Sylvestri, Michael P. Tenney
-
Patent number: 7371689Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: GrantFiled: October 3, 2005Date of Patent: May 13, 2008Assignee: International Business Machines CorporationInventors: Terence L Kane, Darrell L Miles, John D Sylvestri, Michael P Tenney
-
Patent number: 7205237Abstract: Apparatus for exposure and probing of features in a semiconductor workpiece includes a hollow concentrator for covering a portion of the workpiece connected by a gas conduit to a supply of etchant gas. A stage supports and positions the semiconductor workpiece. Control means moves the stage and the semiconductor workpiece to the series of positions sequentially. An energy beam source directs a focused energy beam through an aperture through the concentrator onto a region on the surface of the workpiece in the presence of the etchant gas. The control means moves the stage to a series of positions with respect to the concentrator and the energy beam to direct the energy beam in the presence of the etchant gas to expose a series of regions on the surface of the semiconductor workpiece positioned below the hollow interior space of the concentrator, sequentially.Type: GrantFiled: July 5, 2005Date of Patent: April 17, 2007Assignee: International Business Machines CorporationInventors: Andrew Deering, Terence L. Kane, Philip V. Kaszuba, Leon Moszkowicz, Carmelo F. Scrudato, Michael Tenney