Abstract: A storage element (100, 200) is capable of statically storing a dynamic input signal, and providing that static signal to dynamic logic gates. The element receives at least two input logic signals (150, 170), one of which is a dynamic signal (150) that may be one wire of a 1-of-N signal used in FAST14 logic from a dynamic logic gate (72) that may be a NDL gate, and generates one or more static logic output signals (190, 192). The element, which may or may not receive a clock signal (160), holds its outputs until its dynamic input (150) switches value on a subsequent evaluate cycle and at least one other input, which may be a write enable signal (170), changes signal value. In an alternative embodiment (200), the element may not change output values until a reset signal (330) is received during a prior clock cycle.

Abstract: A logic device with improved capacitance isolation and a design methodology that reduces parasitic capacitance is disclosed. The logic device includes a virtual ground node, a plurality of input signals that may be individual wires of one or more N-NARY signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors gated by the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, the discharge paths are perfectly isolated from each other for every combination of inputs. In another embodiment, intermediate nodes on discharge paths maybe electrically coupled to the evaluation path only at the intermediate node coupled to the virtual ground node.

Abstract: A static output signal is generated using a static storage element (104) and transmitted to a NDL gate (110) over a transmission path (112) that is characterized by a user-specified multi-cycle timing constraint that is used to create appropriate verification tests of the apparatus. The multi-cycle timing constraint may be a pragma that is interpreted by the compiler of a timing analysis tool such as PATHMILL to automatically check the set-up and hold times of the static signal relative to the rising edge or falling edge of user-specified clock signal pulses. The same pragma is interpreted by the compiler of a functional verification tools such as VIS to create statements that test the behavior of the apparatus during the clock signal pulses other than the user-specified clock signal pulses tested by the timing analysis tool.

Abstract: The present invention comprises a method and apparatus for a pipeline of functional units with a late pipe functional unit that executes instructions without stalling until the result is available. The present invention comprises one or more earlier functional units coupled to a late pipe functional unit. The late pipe functional unit does not begin executing instructions until all of the input operands are or will be available for execution so that the late pipe functional unit will execute instructions without stalling until the result will be available in a fixed number of cycles. The present invention further comprises a late pipe functional unit that may comprise a floating point unit, a graphics unit, or an enhanced floating point unit. And finally, the late pipe functional unit is non-stalling and or is non-cancelable.

Abstract: The present invention discloses an apparatus and method for determining the speed of a logic circuit relative to the clock. The preferred embodiment utilizes dynamic logic to deliver a critical signal to a transition detection circuit, which performs the OR/NOR function on the signals. In one embodiment the transition detection circuit comprises static logic. In another embodiment, the transition detection circuit comprises an N-NARY gate that performs the OR/NOR function.

Abstract: The present invention discloses a method and apparatus that uses extensions to the TLB entry to dynamically identify pages of memory that can be weakly ordered or must be strongly ordered and enforces the appropriate memory model on those pages of memory. Such identification and memory model enforcement allows for more efficient execution of memory instructions in a hierarchical memory design in cases where memory instructions can be executed out of order. From the page table, the memory manager constructs TLB entries that associate page frame numbers of memory operands with page-granular client usage data and a memory order tag. The memory order tag identifies the memory model that is currently being enforced for the associated page of memory. The memory manager updates the memory order tag of the TLB entry in accordance with changes in the client usage information. In the preferred embodiment, the TLB structure is a global TLB shared by all processors.

Abstract: A design tool to support design of a N-NARY logic circuit is described. The designer develops a syntax statement that comprises encoded information according to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the N-NARY logic circuit and the specific configuration of transistors required to build the N-NARY logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the N-NARY circuit and a physical circuit description of the N-NARY circuit.

Abstract: The present invention is an apparatus that supports multiple assignment code, comprising a register that may be assigned multiple values, instructions that receive a value and dispatch a result, a first queue that stores the results of an instruction during a pipeline stall, and a second queue that stores the state of the register when an interrupt is taken. The value assigned to a register may be available for processing only after a latency period has passed. The value received by an instruction from a register is the most recent value assigned to the register for which the latency period has passed. The first queue eliminates the need for global stalls in the context of various pipeline implementations. The second queue allows for interruptibility. The present invention further comprises a mode where the software identifies that it does not intend to exploit multiple assignment code.

Abstract: The present invention discloses an apparatus and method for determining the speed of a logic circuit relative to the clock. The preferred embodiment utilizes dynamic logic to deliver a critical signal to a transition detection circuit, which performs the OR/NOR function on the signals. In one embodiment the transition detection circuit comprises static logic. In another embodiment, the transition detection circuit comprises an N-NARY gate that performs the OR/NOR function. The output of the transition detection circuit is fed into a series of delayed flip-flop latches, which determine when the critical signal transitioned from the pre-charge state relative to the clock.

Abstract: A design tool to support design of logic circuits is described. The designer develops a syntax statement that comprises encoded information to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the logic circuit and the specific configuration of transistors required to build the logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the logic circuit and a physical circuit description of the logic circuit.

Abstract: The present invention comprises a multi-function shifter that uses N-nary logic and includes an operation selection and various 1-of-N multiplexers to support a variety of shift modes. The shift modes include rotates, logical shifts in which 0 is shifted into any vacated bit positions, and arithmetic shifts in which the value of the original most significant bit is shifted into any vacated bit positions. The present invention includes a general 32-bit shifter that can shift an arbitrary number of places in a single cycle, using any of the modes described above.

Abstract: The present invention comprises a master global clock distributed in a low-skew manner over a relevant clock domain area coupled with a plurality of locally generated clocks in said clock domain area. The plurality of locally generated clocks are tuned to allow for skew and jitter tolerance. The present invention further comprises embodiments with 3, 4, 5, and 6 locally generated clocks.

Abstract: A syntax statement describing an N-NARY or a CMOS logic circuit having one, and only one, possible configuration of transistors is disclosed. The syntax statement comprises a signal naming convention and one or more gate instantiations using a gate instantiation syntax that includes one or more gate output signal variables described using the signal naming convention, one or more gate operators, and one or more gate expressions using a gate expression syntax that is interpreted to describe the specific transistor configuration of the logic circuit. The signal naming convention includes one or more of the following fields: optional bit and descriptor, signal degree, evaluation, and clock phase. The gate expression syntax further comprises one or more of the following syntaxes: mux select, arithmetic, logical, multiple output, capacitance isolation, or shared node.

Abstract: The described multiplier provides the signed or unsigned product of a multiplicand and multiplier represented in preferably 1-of-4 N-NARY signals by performing a preferably radix-four Booth recoding of the multiplier, producing partial products using a plurality of Booth multiplexers, summing the partial productsto produce two intermediate partial products using a six-level Wallace tree, and summing the two intermediate partial products using a carry lookahead adder. The Booth encoding is performed at the dit level using encoding circuitry implemented in N-NARY logic.

Abstract: An enhanced floating point unit that supports floating point, integer, and graphics operations by combining the units into a single functional unit is disclosed. The enhanced floating point unit comprises a register file coupled to a plurality of bypass multiplexers. Coupled to the bypass multiplexers are an aligner and a multiplier. And, coupled to the multiplier is an adder that further couples to a normalizer/rounder unit. The normalizer/rounder unit may comprise a normalizer and a rounder coupled in series and or a parallel normalizer/rounder. The enhanced floating point unit supports both integer operations and graphics operations with one functional unit.

Abstract: The present invention is a method and apparatus that synchronizes logic in an integrated circuit (IC). The present invention discloses a global clock signal with a global phase and an approximately 50% duty cycle. Additionally, the present invention discloses a first local clock signal with a first phase and an approximately 50% duty cycle that couples to a first dynamic logic gate where the first local clock signal is generated from the global clock signal. One or more intermediate local clock signals with one or more intermediate phases are generated from the global clock signal where each intermediate local clock signal has an approximately 50% duty cycle that couples to one or more intermediate dynamic logic gates. An end local clock signal with an end phase and an approximately 50% dutycycle that is also generated from the global clock signal and that couples to an end dynamic logic gate.

Abstract: The present invention discloses a method and apparatus that uses extensions to the TLB entry to dynamically identify pages of memory that can be weakly ordered or must be strongly ordered and enforces the appropriate memory model on those pages of memory. Such identification and memory model enforcement allows for more efficient execution of memory instructions in a hierarchical memory design in cases where memory instructions can be executed out of order. From the page table, the memory manager constructs TLB entries that associate page frame numbers of memory operands with page-granular client usage data and a memory order tag. The memory order tag identifies the memory model that is currently being enforced for the associated page of memory. The memory manager updates the memory order tag of the TLB entry in accordance with changes in the client usage information. In the preferred embodiment, the TLB structure is a global TLB shared by all processors.

Abstract: The present invention is a method and apparatus for an N-NARY logic circuit that uses N-NARY signals. The present invention includes a shared logic tree circuit that evaluates one or more N-NARY input signals and produces an N-NARY output signal. The present invention additionally includes a first N-NARY input signal coupled to the shared logic tree circuit and a second N-NARY input signal coupled to the shared logic tree circuit. The shared logic circuit evaluates the first second and second N-NARY input signal and produces an N-NARY output signal coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals, 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.

Abstract: The present invention allows the logic state of a clocked precharge (CP) logic gate to be tested when stopping or starting the logic gate's clock and comprises a plurality of clock signals with overlapping phases and a plurality of CP logic gates coupled in series. Each CP logic gate of the plurality of CP logic gates is coupled to an individual clock signal. The present invention further comprises one or more signal keeper devices coupled to certain individual CP logic gates in the critical path of the logic state. The signal keeper device allows the state of the plurality of CP logic gates to be tested when stopping or starting the individual clock signal of an individual logic gate of said plurality of logic gates. The present invention is suitable for a variety of testing techniques that includes IDDQ, scan testing, and hardware emulation testing.

Abstract: The present invention is a method and apparatus of routing a 1 of 4 signal to reduce the effective signal coupling between the signal wires. The present invention is a wire pack with a first, second, third, and fourth wire for routing a 1 of 4 signal in a semiconductor device. While routing the wires of the wire pack, the present invention rotates the route of each individual wire to reduce the signal coupling between the wires. Additionally, an isolation barrier borders the outside of the wire pack to further reduce the signal coupling. The rotation of the wires allow each individual wire to be adjacent to each other wire for ½ of the wire's route.