Abstract: The present invention is a method and apparatus of routing a 1 of N signal to reduce the effective signal coupling between the signal wires. The present invention is a wire pack with a plurality of wires for routing a 1 of N signal in a semiconductor device. While routing the wires of the wire pack, the present invention rotates the route of each individual wire to reduce the signal coupling between the wires. Additionally, an isolation barrier borders the outside of the wire pack to further reduce the signal coupling. The rotation of the wires allow each individual wire be adjacent to each other wire for part of the wire's route. Other embodiments of the present invention include routing 1 of 3 signals and 1 of 4 signals.

Abstract: The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate node and a second evaluate node. Additionally, the logic device comprises a first input signal that has a first input wire and a second input wire where the first input wire corresponds to a first possible value of the first input signal and the second input wire corresponds to a second possible value of the first input signal. The logic device further comprises a first plurality of intermediate nodes that includes a first intermediate node. Additionally, the logic device includes a first plurality of transistors that further includes a first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal.

Abstract: The present invention comprises a plurality of clock signals with an approximately 50% duty cycle and overlapping phases. The phases of the plurality of clocks are such that the phase of an individual clock signal overlaps the phase of an earlier clock signal by an amount equal to the overlap of the phase of the next clock signal. The present invention further comprises a plurality of clocked precharge (CP) logic gates coupled in series. An individual CP logic gate couples to an individual clock signal though the CP logic gate's evaluate device. For the data flow through the individual CP logic gate, the logic gate receives its data input from an earlier CP logic gate in the series and passes to the next CP logic gate in the series. The earlier CP logic gate couples to an earlier phase clock signal, and the next CP logic gate couples to the next phase clock signal.

Abstract: The present invention is a method and apparatus for a register cell that is configured to store more than one bit of information. The cell includes a multiplexer that is configurable to select various inputs when the multiplexer is in various states. The multiplexer is configurable to select a first input when the multiplexer is in a first state, and to select a second input when the multiplexer is in a second state. The multiplexer is further configured to provide multi-bit storage data, the first input being configured to receive multi-bit data from outside the cell. An output element, such as a second multiplexer, is configured to receive a word enable. The output of the first multiplexer is delayed in a delay element, and is provided as one of the inputs to the first multiplexer.

Abstract: The present invention comprises a method and apparatus for a logic circuit with constant power consumption. The logic circuit comprises a 1 of P first input signal that further comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. The logic circuit additionally comprises a 1 of Q second input signal that comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. A logic tree circuit couples to the first input signal and the second input signal. The logic tree circuit generates a result for a 1 of R output signal, which couples to the logic tree circuit. The 1 of R output signal comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. The power consumption of the logic circuit is independent of the value of the first signal or the second signal, which results in the logic circuit having constant power consumption.

Abstract: The present invention is a method and apparatus for a register cell that is configured to store information. The cell includes a multiplexer that is configurable to select various inputs when the multiplexer is in various states. The multiplexer is configurable to select a first input when the multiplexer is in a first state, and to select a second input when the multiplexer is in a second state. The multiplexer is further configured to provide storage data, the first input being configured to receive data from outside the cell. An output element, such as a second multiplexer, is configured to receive a word enable. The output of the first multiplexer is delayed in a delay element, and is provided as one of the inputs to the first multiplexer.

Abstract: The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.

Abstract: The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.

Abstract: A method and system in a data processing system are disclosed for efficiently managing an indication of a status of each of a plurality of registers included with the data processing system. An array is established having multiple entry fields for storing multiple entries. Each of the multiple entry fields is associated with a different one of the plurality of registers. A status of each of the plurality of registers is determined. A plurality of partitions are established within the array. Each of the partitions are concurrently accessible by the data processing system. A plurality of the multiple entry fields are associated with one of the plurality partitions. An entry is stored in each of the multiple entry field. The entry includes the status of each of the plurality of registers. Each entry is associated with one of the partitions so that a plurality of the multiple entries may be concurrently accessed.

Abstract: An apparatus for handling special cases outside of normal floating-point arithmetic functions is provided that is used in a floating-point unit used for calculating arithmetic functions. The floating-point unit generates an exponent portion and a mantissa portion and a writeback stage is coupled to the exponent portion and to the mantissa portion and is specifically used to handle the special cases outside the normal float arithmetic functions. A spill stage is also provided and is coupled to the writeback stage to receive a resultant exponent and mantissa. A register file unit is coupled to the writeback stage and the spill stage through a plurality of rename busses, which are used to carry results between the writeback stage and spill stage and the register file. The spill stage is serially coupled to the writeback stage so as to provide a smooth operation in the transition of operating on the results from the writeback stage for the exponent and mantissa.

Abstract: The present invention is directed toward an combined decoder/adder circuit which provides faster access to a cache in a microprocessor than implementations which include an adder circuit which is followed by a decoder circuit. By decoding the upper order bits of a first operand and then rotating the upper order bits of the first operand by the upper order bits of a second operand, followed by an additional shift by one which is enabled by a carry generator the overall speed of the critical path is greatly increased. Accordingly, the time needed for generating an effective address (EA) and therefore accessing the cache is significantly decreased. The present invention has significant utility in microprocessors in which the word line decode is the critical path.

Abstract: A method and system for distributed instruction address translation in a multiscalar data processing system having multiple processor units for executing multiple tasks, instructions and data stored within memory at real addresses therein and a fetcher unit for fetching and dispatching instructions to the processor units. A memory management unit (MMU) is established which includes a translation buffer and translation algorithms for implementing page table and address block type translations of every effective address within the data processing system into real addresses within memory. A translation array, which includes a small number of translation objects for translating effective addresses into real addresses, is then established within the fetcher unit. The translation objects are periodically and selectively varied, utilizing the translation capability of the memory management unit (MMU), in response to a failure to translate an effective address into a real address within the fetcher unit.

Abstract: A method and system are disclosed for implementing floating point exception enabled operation without substantial performance degradation. In a multiscalar processor system, multiple instructions may be issued and executed simultaneously utilizing multiple independent functional units. This is typically accomplished utilizing separate branch, fixed point and floating point processor units. Floating point arithmetic instructions within the floating point processor unit may initiate one of a variety of exceptions associated within invalid operations and as a result of the pipelined nature of floating point processor units an identification of which instruction initiated the exception is not possible. In the described method and system, an associated dummy instruction having a retained instruction address is dispatched to the fixed point processor unit each time a floating point arithmetic instruction is dispatched to the floating point processor unit.

Abstract: A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.