Patents by Inventor Terrance J. Dishongh

Terrance J. Dishongh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7886809
    Abstract: In one embodiment, an apparatus includes a phase change material, a plurality of particles intermixed with the phase change material, and a conductive structure encapsulating the phase change material. The conductive structure includes a cavity including a cone shape. In one embodiment, a method includes forming a conductive structure having a cavity, injecting a phase change material into the cavity, injecting a plurality of spheres into the cavity, and sealing the cavity.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 15, 2011
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, David Pullen
  • Patent number: 7791585
    Abstract: A method of fabricating a flexible display, the method comprising selecting a first flexible sheet and a second flexible sheet; and forming a number of magnetic display elements having magnetically controllable reflectivity between the first flexible sheet and the second flexible sheet. In some embodiments, a display includes pixels having a magnetically controllable reflectivity. The pixels are formed between a pair of flexible non-conductive sheets. Each of the magnetically controllable pixels includes a flexible ring located between the flexible non-conductive sheets. Each of the magnetically controllable pixels also includes magnetic particles located within the flexible ring. The location of the magnetic particles with respect to the flexible non-conductive sheets determines the reflectivity of the pixel. The display is especially suitable for use in connection with portable electronic devices.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: James D. Jackson, Terrance J. Dishongh, Damion T. Searls
  • Patent number: 7663490
    Abstract: A wearable data processing system includes a high power radio module and a low power radio module. The high power radio module may retrieve data from radio frequency identifier (RFID) tags. The low power radio module may transmit data to a base station data pertaining to the detected RFID tags. The low power radio module may also receive a power management signal from a gate radio. The gate radio may have an adjustable range. A power management engine in the wearable data processing system may determine whether the low power radio module is receiving the power management signal from the gate radio. The power management engine may also activate and deactivate the high power radio module, depending on whether the low power radio module is receiving the power management signal from the gate radio. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventor: Terrance J. Dishongh
  • Publication number: 20090085721
    Abstract: A wearable data processing system includes a high power radio module and a low power radio module. The high power radio module may retrieve data from radio frequency identifier (RFID) tags. The low power radio module may transmit data to a base station data pertaining to the detected RFID tags. The low power radio module may also receive a power management signal from a gate radio. The gate radio may have an adjustable range. A power management engine in the wearable data processing system may determine whether the low power radio module is receiving the power management signal from the gate radio. The power management engine may also activate and deactivate the high power radio module, depending on whether the low power radio module is receiving the power management signal from the gate radio. Other embodiments are described and claimed.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventor: Terrance J. Dishongh
  • Patent number: 7512486
    Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises acquiring vehicle fuel consumption information from a plurality of geographic locations, compiling the information to a map, and creating a low fuel consumption path between two locations on the map using the information.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: Bradford H. Needham, Terrance J. Dishongh, Kevin S. Rhodes
  • Patent number: 7316265
    Abstract: In one embodiment, a method includes forming a conductive structure having a cavity, injecting a phase change material into the cavity, injecting a plurality of spheres into the cavity, and sealing the cavity.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: January 8, 2008
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, David Pullen
  • Patent number: 7271349
    Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Rebecca A. Jessep, Terrance J. Dishongh, Carolyn R. McCormick, Thomas O. Morgan
  • Patent number: 7185799
    Abstract: Solder connections are created between the substrate of an electronic package and a circuit board having lengths that are longer than the width. The solder connections are created by locating solder balls of power or ground connections close enough to one another so that, upon reflow to the circuit board the solder balls combine, creating a larger solder connection. Signal solder balls, however, remain separated. The power or ground solder balls on a particular bond pad are separated from one another by portions of a removable solder mask that keep the solder balls spherical in shape during solder ball attachment to the electronic package. However, it is removed prior to reflow to the circuit board, thus creating a larger, longer solder connection between the electronic package and circuit board.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: March 6, 2007
    Assignee: Intel Corporation
    Inventors: Tom E. Pearson, Dudi I. Amir, Terrance J. Dishongh
  • Patent number: 7168164
    Abstract: Methods to shield conductive layer from via. A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: Rebecca A. Jessep, Terrance J. Dishongh, Carolyn R. McCormick, Thomas O. Morgan
  • Patent number: 7158111
    Abstract: A display includes pixels having a magnetically controllable reflectivity. The pixels are formed between a pair of flexible non-conductive sheets. Each of the magnetically controllable pixels includes a flexible ring located between the flexible non-conductive sheets. Each of the magnetically controllable pixels also includes magnetic particles located within the flexible ring. The location of the magnetic particles with respect to the flexible non-conductive sheets determines the reflectivity of the pixel. The display is especially suitable for use in connection with portable electronic devices.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: James D. Jackson, Terrance J. Dishongh, Damion T. Searls
  • Patent number: 7041357
    Abstract: Apparatus and methods are presented for reinforcing and stiffening a printed circuit board (PCB) in selected locations by utilizing preferentially oriented fibers. Selected fibers within the polymeric material matrix of the PCB fiber-matrix layer are removed and replaced with a similar quantity of fibers in a preferential orientation. Various combinations of layering of modified fiber-matrix layer material with conventional fiber-matrix layer material are presented to achieve the desired PCB stiffening. Printed circuit boards, under the weight of heavy attached electronic components, may deflect or flex along an axis, defined as the characteristic fold. This flexing is exasperated with manufacturing and handling loading, particularly when mounted in a chassis. Preferentially orientated fibers laid transverse to the characteristic fold reinforces the area to resist flexure within the area surrounding the characteristic fold.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Scott Dixon
  • Patent number: 6996899
    Abstract: Solder bumps are created on a substrate of an electronic assembly having lengths that are longer than the widths. The solder bumps are created by locating solder balls of power or ground connections close to one another so that, upon reflow, the solder balls combine. Signal solder balls however remain separated. Capacitors are created by locating power solder bumps adjacent ground solder bumps and extending parallel to one another.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, James D. Jackson
  • Patent number: 6927346
    Abstract: Apparatus and methods for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect. A first reflowable material is deposited on the VIP bond pad. A sphere having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid, and the first reflowable material preventing the first interconnect material from migrating into the via-in-pad.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: August 9, 2005
    Assignee: Intel Corporation
    Inventors: Carolyn R. McCormick, Terrance J. Dishongh
  • Patent number: 6884939
    Abstract: An electronic assembly is provided, having a capacitor interconnected between BGA solder balls. The capacitor is placed on a motherboard and soldered to the BGA solder balls when the BGA solder balls are soldered to electric lands on the motherboard.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: April 26, 2005
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Tom E. Pearson
  • Patent number: 6882043
    Abstract: According to one aspect of the invention a method of constructing an electronic assembly is provided. The electronic assembly is constructed from a semiconductor package including a package substrate and a semiconductor chip mounted to the package substrate, a thermally conductive member, and a substance including indium. The method comprises securing the thermally conductive member and the semiconductor package in a selected orientation relative to one another with the thermally conductive member on a side of the semiconductor chip opposing the package substrate and with the substance located between the semiconductor chip and at least a portion of the thermally conductive member. The substance is thermally coupled to the semiconductor chip on one side and thermally coupled to the portion of the thermally conductive member on an opposing side.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: April 19, 2005
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Paul W. Churilla, David H. Pullen
  • Patent number: 6878305
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Patent number: 6875367
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: April 5, 2005
    Assignee: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Patent number: 6856016
    Abstract: An embodiment of the present invention described and shown in the specification and drawings is a process and a package for facilitating cooling and grounding of a semiconductor die using carbon nanotubes in a thermal interface layer between the die and a thermal management aid. The embodiments that are disclosed have the carbon nanotubes positioned and sized to utilize their high thermal and electrical conductance to facilitate the flow of heat and current to the thermal management aid. One embodiment disclosed has the carbon nanotubes mixed with a paste matrix before being applied. Another disclosed embodiment has the carbon nanotubes grown on the surface of the semiconductor die.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: February 15, 2005
    Inventors: Damion T. Searls, Terrance J. Dishongh, James Daniel Jackson
  • Publication number: 20040256133
    Abstract: An electronic assembly is provided, having a capacitor interconnected between BGA solder balls. The capacitor is placed on a motherboard and soldered to the BGA solder balls when the BGA solder balls are soldered to electric lands on the motherboard.
    Type: Application
    Filed: June 18, 2003
    Publication date: December 23, 2004
    Inventors: Terrance J. Dishongh, Tom E. Pearson
  • Publication number: 20040238216
    Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.
    Type: Application
    Filed: July 8, 2004
    Publication date: December 2, 2004
    Inventors: Rebecca A. Jessep, Terrance J. Dishongh, Carolyn R. McCormick, Thomas O. Morgan