Patents by Inventor Terrance J. Dishongh

Terrance J. Dishongh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6818155
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: November 16, 2004
    Assignee: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Patent number: 6803527
    Abstract: A circuit board apparatus and a method for a circuit board. An embodiment of a circuit board includes a first layer and a second layer; a substrate between the first layer and the second layer; a first surface mount device pad on the first layer of the substrate; a first via, the first via being formed partially or wholly through a first end of the first surface mount device pad, the first via passing through the substrate between the first layer and the second layer; a second surface mount device pad adjacent to the first surface mount device pad; and a second via, the second via being formed partially or wholly through a first end of the second surface mount device pad, the second via passing through the substrate, the first end of the first surface mount device pad being the end of the first surface mount device pad that is the farthest from the first end of the second surface mount device pad.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: October 12, 2004
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Bryce Horine
  • Patent number: 6793505
    Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Weston C. Roth, Damion T. Searls
  • Patent number: 6793503
    Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Weston C. Roth, Damion T. Searls
  • Patent number: 6774310
    Abstract: An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: August 10, 2004
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Prateek J. Dujari, Bin Lian, Damion T. Searls
  • Publication number: 20040131824
    Abstract: Apparatus and methods are presented for reinforcing and stiffening a printed circuit board (PCB) in selected locations by utilizing preferentially oriented fibers. Selected fibers within the polymeric material matrix of the PCB fiber-matrix layer are removed and replaced with a similar quantity of fibers in a preferential orientation. Various combinations of layering of modified fiber-matrix layer material with conventional fiber-matrix layer material are presented to achieve the desired PCB stiffening. Printed circuit boards, under the weight of heavy attached electronic components, may deflect or flex along an axis, defined as the characteristic fold. This flexing is exasperated with manufacturing and handling loading, particularly when mounted in a chassis. Preferentially orientated fibers laid transverse to the characteristic fold reinforces the area to resist flexure within the area surrounding the characteristic fold.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 8, 2004
    Applicant: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Scott Dixon
  • Publication number: 20040118606
    Abstract: Apparatus and methods providing for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect is presented. In one embodiment in accordance with the invention, a first reflowable electrically conductive interconnect material is deposited on the VIP bond pad. A sphere comprising an electrically conductive material having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid. A second electrically conductive interconnect material having a reflow temperature lower than the melt temperature of the sphere is deposited on the component interconnect and a second reflow process is performed to interconnect the sphere to the component interconnect while the sphere remains solid, effectively preventing the second interconnect material from migrating into the plated though hole.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Inventors: Carolyn R. McCormick, Terrance J. Dishongh
  • Patent number: 6752204
    Abstract: An iodine-containing thermal interface material disposed between a heat source and a heat dissipation device.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: June 22, 2004
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Prateek J. Dujari, Bin Lian, Damion Searls
  • Publication number: 20040109974
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Application
    Filed: October 28, 2003
    Publication date: June 10, 2004
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Publication number: 20040084210
    Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.
    Type: Application
    Filed: July 22, 2003
    Publication date: May 6, 2004
    Inventors: Terrance J. Dishongh, Carolyn R. McCormick
  • Publication number: 20040087173
    Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.
    Type: Application
    Filed: October 28, 2003
    Publication date: May 6, 2004
    Inventors: George Hsieh, Terrance J. Dishongh, Norman J. Armendariz, David V. Spaulding
  • Patent number: 6730860
    Abstract: Solder bumps are created on a substrate of an electronic assembly having lengths that are longer than the widths. The solder bumps are created by locating solder balls of power or ground connections close to one another so that, upon reflow, the solder balls combine. Signal solder balls however remain separated. Capacitors are created by locating power solder bumps adjacent ground solder bumps and extending parallel to one another.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, James D. Jackson
  • Publication number: 20040017295
    Abstract: An electrically modifiable label. In some embodiments, an electrically modifiable label may be applied to or form a part of products that have configurable or otherwise dynamic characteristics. That is, characteristics or desirability that vary over time or characteristics that may be selected or determined at or after advanced stages of manufacturing processes.
    Type: Application
    Filed: July 16, 2003
    Publication date: January 29, 2004
    Inventors: Terrance J. Dishongh, Damion T. Searls, Bin Lian
  • Patent number: 6682802
    Abstract: Apparatus and methods are presented for reinforcing and stiffening a printed circuit board (PCB) in selected locations by utilizing preferentially oriented fibers. Selected fibers within the polymeric material matrix of the PCB fiber-matrix layer are removed and replaced with a similar quantity of fibers in a preferential orientation. Various combinations of layering of modified fiber-matrix layer material with conventional fiber-matrix layer material are presented to achieve the desired PCB stiffening. Printed circuit boards, under the weight of heavy attached electronic components, may deflect or flex along an axis, defined as the characteristic fold. This flexing is exasperated with manufacturing and handling loading, particularly when mounted in a chassis. Preferentially orientated fibers laid transverse to the characteristic fold reinforces the area to resist flexure within the area surrounding the characteristic fold.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: January 27, 2004
    Assignee: Intel Corporation
    Inventors: George Hsieh, Terrance J. Dishongh, Scott Dixon
  • Publication number: 20040005736
    Abstract: An embodiment of the present invention described and shown in the specification and drawings is a process and a package for facilitating cooling and grounding of a semiconductor die using carbon nanotubes in a thermal interface layer between the die and a thermal management aid. The embodiments that are disclosed have the carbon nanotubes positioned and sized to utilize their high thermal and electrical conductance to facilitate the flow of heat and current to the thermal management aid. One embodiment disclosed has the carbon nanotubes mixed with a paste matrix before being applied. Another disclosed embodiment has the carbon nanotubes grown on the surface of the semiconductor die.
    Type: Application
    Filed: July 2, 2002
    Publication date: January 8, 2004
    Applicant: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, James Daniel Jackson
  • Patent number: 6672370
    Abstract: A heat sink includes a heat sink body including a number of fins and a cavity for holding a phase change material and a number of particles to enhance the mixing of the phase change material during the operation of the heat sink. In operation, the body of the heat sink conducts thermal energy to the phase change material. The energy is absorbed during the phase change of the phase change material. After absorbing energy and changing to a liquid state, the phase change material continues to dissipate energy by convection. The convection currents in the cavity are directed by the shape of the cavity surfaces and enhanced by the particles intermixed with the phase change material.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: January 6, 2004
    Assignee: Intel Corporation
    Inventors: Damion T. Searls, Terrance J. Dishongh, David Pullen
  • Publication number: 20030207598
    Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.
    Type: Application
    Filed: May 27, 2003
    Publication date: November 6, 2003
    Inventors: Terrance J. Dishongh, Weston C. Roth, Damion T. Searls
  • Patent number: 6630631
    Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: October 7, 2003
    Assignee: Intel Corporation
    Inventors: Terrance J. Dishongh, Carolyn R. McCormick
  • Publication number: 20030183421
    Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 2, 2003
    Inventors: Terrance J. Dishongh, Carolyn R. McCormick
  • Publication number: 20030183420
    Abstract: According to the invention, an embodiment of a circuit board includes a substrate having a first layer and a second layer; a surface mount device pad on the first layer of the substrate; and a via, the via being formed wholly or partially through the surface mount device contact and passing through the substrate between the first layer and the second layer.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Inventors: Terrance J. Dishongh, Bryce D. Horine