Abstract: A digital computer which includes a memory refresh system for controlling the generation and sequencing of refresh signals to a memory subsystem comprised of at least one memory unit having a plurality of slots each capable of receiving a dynamic random access memory bank therein. The memory refresh system includes means for generating refresh signals and at least one independent refresh sequence controller for efficiently controlling the sequence in which the memory banks associated with a particular refresh sequence controller receive refresh signals. Each refresh sequence controller controls a combination of multi-stage shift registers for issuing refresh signals to memory banks installed on the corresponding memory unit and multi-stage shift registers for providing wait cycles during which refresh signals are being generated by other independent refresh sequence controllers.

Abstract: A method and apparatus which enables circuitry to detect and take advantage of the intrinsic performance or delay characteristic of the respective device in which the circuitry is embedded. By determining the delay characteristics of the device and sampling signals based on this information, the circuitry may not be required to wait for additional clock cycles which is required for logic in prior art devices which do not take advantage of the device's intrinsic performance. This considerably increases device performance. A device delay encoder circuit included in a device encodes the instantaneous delay coefficient of the device in question and a clocking signal is used to determine whether the delay elements should be considered fast or slow. All of the logic circuitry on a chip have a similar derating factor, and thus the performance of the delay elements is indicative of the performance of the entire chip.

Abstract: A digital processor system is disclosed that employs a bus bridge interfacing a primary bus to a secondary bus and which includes a transaction backoff signal line that provides an economical method of providing split transactions between the busses, of preventing deadlock situations between the busses, and of providing strong lock ordering across the busses. A primary bus master is backed-off the bus if it is attempting to access a device resident on the secondary bus and if mastership of the secondary bus cannot be attained by the bus bridge within a certain latency. The bus bridge further implements a method of prefetching read data from a device resident on the secondary bus in response to a primary bus master being backed-off the primary bus during a read operation.

Abstract: A bus with selective burst ordering enables the implementation of computer systems that incorporate bus masters (e.g., processors, DMA controllers, LAN controllers, etc.) with dissimilar burst orders. The same bus supports devices which require or prefer differing burst orders for high bandwidth data transfers. Selective burst order is enabled through the use of a bus line which may be asserted by the current bus master. By asserting the corresponding signal, a current bus master indicates that sequential (rather than non-sequential) burst order will be used for data transfer. Specialized burst address generation logic enables a bus slave to generate, in the selected burst order, the low order bits of memory addresses for the data words implicitly addressed during a burst transfer.

Abstract: A memory mapping scheme for a computer system includes a number of slave devices attached to a system bus, which slave devices have partitioned among themselves a memory address storage system. The memory address storage system is, in turn, divided into a number of regions. The memory mapping scheme also includes a subsystem for mapping the regions, which subsystem includes a unique subtractive descriptor that disjunctively allows mapping of regions that reside on only one of a number of input/output channels connected to the system bus.

Abstract: A caching disk controller is provided which includes a bus bridge that forms an interface between a memory of the disk controller and a host computer. The caching disk controller further includes a SCSI processor for controlling the transfer of data from a SCSI disk drive to the memory via a local bus. A zero latency DMA controller embodied within the bus bridge snoops the local bus as data is being transferred from the SCSI disk drive to the memory, and thereby allows the data to be sequentially latched within a data FIFO of the bus bridge concurrently with its transfer into the memory. As a result, the requested data may be advantageously provided from the bus bridge to the host computer with reduced delay, while the data continues to be stored within the memory to accommodate high hit rates during subsequent transfers.

Abstract: A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.

Abstract: A device for interfacing an expansion bus with an option card and an associated method for initializing a computer system having the option card installed on the expansion bus thereof. The interface device includes a dual ported RAM having a first port coupled to the expansion bus and a second port coupled to the option card, a processor coupled to the second port of the dual ported RAM and a non-volatile memory coupled to the processor and to the second port of the dual ported RAM. At power up, the processor transfers an expansion BIOS and pattern stored in the non-volatile memory to first and second portions, respectively, of the memory space of the dual ported RAM. The computer system scans the second portion of the dual ported RAM for the pattern, executes a first initialization sequence contained in the expansion BIOS upon detecting the pattern and then executes a second initialization sequence contained in a BIOS of the computer system.

Abstract: A store queue is provided that forms an interface between a primary bus and a secondary bus and which temporarily stores data to be written via a memory or I/O channel to a peripheral device. The store queue allows partial writes executed on the primary bus to be combined within a common word storage cell of an internal FIFO buffer regardless of whether the consecutive partial writes result in an invalid byte combination. If the data being transferred does not constitute an invalid byte combination, the store queue executes a single write cycle on the secondary bus. If the data contained by the word memory cell constitutes an invalid byte combination, the store queue executes two or more partial writes on the secondary bus to transfer the data in the order it was received. The store queue includes a byte order tracking circuit, such as an accumulation counter, for tracking the order in which the bytes are written from the primary bus.

Abstract: A combined multiprocessor interrupt controller and interprocessor communication mechanism includes a system bus, an input/output bridge element coupled to the system bus, and a system controller coupled to the system bus. The input/output bridge element includes circuitry for receiving interrupt requests, for obtaining processor-associated vectors, and for packaging obtained processor-associated vectors into interprocessor communication messages. The system controller includes circuitry for receiving and decoding interprocessor communication messages, and for providing processor-associated vectors to the associated processor.

Abstract: A digital computer system includes an interface for routing data which permits the transfer of data between mismatched devices. The computer system comprises a processor, memory and an interconnecting data bus, all configured to handle data units of a first data width. Also connected to the data bus is at least one I/O device configured to handle data units of a second data width. By adjusting the width of the data being transferred to match the width of the receiving device or bus, data may be transferred between devices of differing width. To adjust the width, control means are provided which modify the route along which data bytes are transferred based upon the width of the transferring and receiving devices and the direction of transfer are provided.

Abstract: A method and apparatus for reducing the latency of TLB and segment descriptor reloads by eliminating the extra read/write cycles normally required for these accesses. The CPU includes special cycles which perform segment descriptor and TLB reloads using only one cycle. The memory controller includes logic which returns the requested data back to the processor and, in addition, performs the required status bit modification. Therefore, the read/write cycle that was required in prior art designs to perform this status update is not required, but rather only a single read cycle is necessary to perform the same operation. In one embodiment, the memory controller includes logic which only performs the write to set the respective status bits in the case where the appropriate bits are not already set. This reduces the latency of subsequent memory cycles. In another embodiment, the memory controller asserts a completion signal back to the CPU to indicate that it has updated the status bits in the respective entry.

Abstract: A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.

Abstract: A display scrolling system for a personal digital assistant (PDA) which includes a display screen disposed on a top surface of the PDA and a mouse integrated into the bottom surface of the PDA. Documents to be displayed on the screen are stored in a memory of the PDA. The PDA is placed on a work surface such that the mouse is manipulated by rolling the PDA across the surface. The work surface is regarded by the PDA as a virtual display of the document to be displayed on the display screen. As the PDA is rolled across the surface, the mouse generates translation information to a memory controller, which determines the location of the PDA with respect to the virtual document and generates viewport coordinates, which define a portion of the document to be displayed on the display screen. The viewport coordinates are input to a memory controller, which generates memory addresses to the memory indicating the location in the memory of the document portion defined by the viewport coordinates.

Abstract: Method and apparatus for power management of a RAM subsystem of a computer. Blocks of data stored at various addresses throughout the RAM subsystem are packed into unallocated memory space at the lowest possible physical location within the RAM subsystem and then are compressed. The packed and compressed data is then copied into the minimum number of RAM devices comprising the subsystem needed to store such data. The remaining RAM devices are either deenergized, if they comprise static RAM, or not refreshed, if they comprise dynamic RAM, thereby reducing the power consumption of the subsystem. Upon a command to return from the reduced power consumption mode, the above steps are executed in the reverse order and the blocks of data are copied to their original memory address locations in said RAM subsystem, using a table that is compiled during the packing step.

Abstract: A system for connecting a plurality of input/output (I/O) channels to a single computer system bus. A system controller establishes priority among the I/O channels competing for access to the system bus. A plurality of I/O channel bridges are connected to the system bus and interface with EISA channels. The I/O bridges receive data from the EISA channels at one data rate and transmit the data to the system bus at another data rate. Data is stored within the I/O bridges in a cache memory device until commanded to transmit the data to the system bus by the system controller.

Abstract: An improved read ahead strategy that improves the performance of a disk array subsystem. The disk controller keeps track of the last n reads to the array. If a new read request is received that is adjacent to any of the last n reads, the controller performs a look ahead read because a sequential read may be in progress. The parameter n is preferably set comparable to or greater than the number of maximum independent activites being performed by the computer system. Therefore, in a multithread system, the controller performs a readahead if any one thread is doing a sequential read.

Abstract: A method and apparatus which provides bi-directional communication between a video monitor and a computer system unit. This enables the video monitor to inform the system unit of its capabilities without direct user involvement and also enables the system unit to directly control or adjust all the functions of the video monitor. In the preferred embodiment, bi-directional communication between the video monitor and the system unit is provided utilizing a mouse port in the keyboard controller. Multiplexors are coupled between the mouse port and each of the mouse and video monitor to select between data paths and selectively allow communication between the system unit and the video monitor. Monitor control software is included in the system unit which can be used to control or adjust the output of the video monitor.

Abstract: A pointing device or mouse which monitors motion in both the X and Y directions as well as in the yaw or rotational direction. The pointing device hence monitors three degrees of freedom and thus provides a more accurate indication of the position of the device. One embodiment comprises a pointing device which includes two motion indicators or mouse balls integrated into the bottom of the device which detect change of motion or position in one X and two Y directions. Separate Y measurements are made for each of the respective balls because yaw or rotation of the device causes the line movements for the two balls to differ. The two balls are preferably a distance L apart, and the rotation and translation of the respective balls are measured by the change in position with reference to a center point between the two balls. The two mouse balls generate signals indicating positive or negative motion in the respective directions.

Abstract: This invention relates to the general area of data integrety in digital computers. In particular it relates to digital computer systems having parity checked systems busses and ECC checked memory. This invention increases the performance of such systems by reducing the memory latency incurred in the ECC to parity conversion process.