Abstract: A disk drive array including a controller which provides scatter/scatter (bi-directional scatter/gather) operations between noncontiguous host memory address locations and noncontiguous disk address locations. The host provides a single request to launch a scatter/scatter transfer. The single data request includes a pointer to a list of transfer counts and addresses, the length of the list, and the starting logical address on the disk transfer. Skipped blocks in a scatter/scatter request are specified by data address value of -1, and a no-operation (no-op) request is enqueued for each skipped block. Thus, during reads the controller extends the scattered read from the disk into a single large read of contiguous sectors and suppresses the unwanted data by inserting "no-operation" commands in place of the read commands during the transfer to the host.

Abstract: An improved liquid crystal display (LCD) is provided having a static random access memory located within each liquid crystal control cell and between each display electrode and corresponding bit and word lines. The memory cell, or storage cell, includes a pass-gate transistor which, upon activation via word line, forwards bit line video data to a memory circuit, such as a latching circuit, placed between the pass-gate transistor and the display electrode. The latching circuit may consist of two thin-film transistors connected as cross-coupled inverters for latching video data upon the display electrode for virtually an indefinite period of time or until the pass-gate transistor is again activated. By utilizing a storage cell with buffer capability adjacent each display electrode, problems associated with large data line current can be minimized. Moreover, the static memory can rid the host processor of having to continuously refresh the LCD active matrix.

Abstract: A system for refreshing selected portions of a dynamic access memory (DRAM) subsystem of a computer. A memory controller of the present invention includes a RAM device for storing a plurality of region descriptors used to inhibit the refresh of address ranges of the DRAM that do not contain valid data, thereby conserving energy required to refresh the entire DRAM. The controller includes logic circuitry connected between a refresh period timer and the RAM device for inhibiting receipt by a RAS generator of a refresh pulse when a generated refresh address falls within the refresh address range defined by the region descriptor. A refresh address output by a refresh address counter compared to the region descriptors in the RAM device, and if the region descriptors indicate that the row addressed by the refresh address does not contain valid data, the RAS generator is inhibited from producing a RAS pulse.

Abstract: A method and apparatus which enables devices connected to a bus to detect and take advantage of the early arrival of bus signal inputs. A signal arrival encoder circuit included in a device encodes the arrival time of a signal input whose early arrival is desired to be detected. The arrival time of the signal at issue is categorized according to a desired degree of precision or granularity depending upon the complexity of the encoder used in the respective embodiment. The encoded signal arrival information is then used by the respective device to determine when to sample the other respective input signal. By detecting the early arrival of this input, the device is not required to wait for the worst case signal arrival time to utilize the information. This considerably increases system performance.

Abstract: A memory channel array configuration wherein two or more memory channels are used for data transfer and data is striped across each of the memory channels. In addition, one or more redundant memory channels, preferably a single dedicated parity channel, are used for error correction. In the preferred embodiment the memory channel configuration utilizes RAMBUS based memory channels, and thus the present invention provides error correction for a RAMBUS based memory system. Also, the use of multiple memory channels in conjunction with data striping across each of the channels allows for much higher data transfer bandwidths than is available using prior art implementations of RAMBUS technology.

Abstract: A system for inductively coupling power and data to a portable electronic device. A portable device, such as a personal digital assistant, is powered or recharged via an inductive link between the device and a support unit, thereby eliminating the need for cabling or other connections therebetween. The same inductive link is also used to transfer data signals between the device and a second electronic device, for example, a conventional desktop computer. The support unit includes a primary winding of a transformer, a power amplifier and a modulator. The portable device includes a secondary winding connected in parallel with the input of a rectifier, the output of which is connected to a battery charging circuit, and to a modem, which is further connected to the device microprocessor. Placement of the device on the support unit effects the inductive coupling when the primary and secondary windings are in proximity to one another.

Abstract: A computer system including at least one processor and a cache subsystem, in which computer system locked cycles are generated, include a jumper assembly for operatively connecting the at least one processor and the cache subsystem so as to render locked cycles cacheable if the computer system includes only one processor and non-cacheable if the computer system includes more than one processor. A method according to the present invention includes the steps of determining whether there is one or more than one processor in a computer system, and then rendering locked cycles cacheable or non-cacheable accordingly.

Abstract: A method and apparatus which provides bi-directional communication between a video monitor and a computer system unit. This enables the video monitor to inform the system unit of its capabilities without user involvement and also enables the system unit to directly control or adjust all the functions of the video monitor. In the preferred embodiment, a monitor/mouse interface provides bi-directional communication between the video monitor and the system unit. The monitor/mouse interface connects to the mouse and video connectors or the back of the system unit and in turn connects to the mouse and video monitor. The interface includes separate data paths from the system unit to the mouse and video monitor, respectively. Monitor control software is included in the system unit which can be used to control or adjust the output of the video monitor.

Abstract: An apparatus and method for a computer system having at least two disk drives in a data storage system wherein data may be read from or written to the disk drives simultaneously during a load multiple operation. Data from the disk drives may be simultaneously loaded into two different memory buffers utilizing the maximum available I/O data bus bandwidth.

Abstract: This invention relates to the general area of data integrety in digital computers. In particular it relates to digital computer systems having parity checked systems busses and ECC checked memory. This invention increases the performance of such systems by reducing the memory latency incurred in the ECC to parity conversion process.

Abstract: A content addressable memory (CAM) which is capable of performing string search functions in hardware. The implementation of string search in hardware eliminates the requirement of software to perform this function and thus significantly increases data compression performance. Each byte or memory storage unit of the CAM includes a comparator and a single bit flip-flop. The comparator asserts a match signal to the flip-flop if the contents of a memory storage unit match external data and a prior memory storage unit match signal is asserted. Two types of comparison operations are provided by each memory storage unit. The first ignores the contents of a previous flip-flop, and this comparison operation is used for the first character of a string search. The second type of comparison operation takes into account the value latched in the preceding byte of the CAM. For example, the comparison for byte N only matches if the previous comparison for byte N-1 matched.

Abstract: An apparatus and method for a computer system having at least three disk drives in a storage array in which the rotational speed and angular position of the disk spindles are synchronized. At least two of these disks store data and at least one disk stores parity. All disks have corresponding tracks and sectors, however, the corresponding sectors of the parity disk are skewed in angular position so as to allow adequate time for the disk controller to read existing data from data disk sectors, calculate parity for new data to be written, and write the calculated parity to the corresponding sectors of the parity disk all during the same revolution of the disks.

Abstract: A digital computer system has a central processor unit (CPU) and a store queue facility. The store queue facility receives full digital words or segments thereof (bytes) for intermediate storage prior to storage in an addressable unit such as a dynamic random access memory (DRAM). The store queue facility has a plurality of registers for storing digital words and bytes for storage at different, discreet addresses in the addressable unit. The store queue has circuitry for assembling bytes into a digital word or into a plurality of bytes for ultimate storage in the addressable unit. Some combinations of bytes are not valid and will therefore not be entered together in a single digital word.

Abstract: A liquid crystal display (LCD) of high visual quality and having a high density wiring arrangement is provided. The LCD can accommodate up to four addressing and/or control conductors placed across the display and between columns and rows of display electrodes. If four conductors are utilized, those conductors can be arranged as a stacked pair placed between rows and a stacked pair placed between columns of display electrodes. At areas where one stacked pair of conductors intersect the other, a plurality of cross-over regions exists which provide vias for routing the conductors through the region as well as for connecting the conductors to a control circuit within each region. Each control circuit includes a pass-gate transistor for receiving two addressing conductors and a memory element capable of receiving two power conductors.

Abstract: A computer system includes an accessible memory controller, an accessible cache controller, and circuitry for accessing the accessible memory controller and the accessible cache controller simultaneously. Certain preferred embodiments of the present invention also include a deassertable miss line, that is, a line which when deasserted indicates that the data was found in the cache and that the memory access should be cancelled.

Abstract: A digital computer having a dual path memory retrieval system for a dynamic RAM memory unit comprised of any number of interleaved memory banks. The system includes means for asserting and deasserting an access signal to specified locations of the interleaved memory banks, a multiplexer having a pair of input channels for each memory bank and a pair of data paths from the output of each memory bank to the corresponding input channels of the multiplexer. The first data path is a direct path between the memory bank and a first one of the pair of input channels and the second data path is a latched path between the memory bank and a second one of the pair of input channels.

Abstract: An apparatus and method for a computer system to rapidly access at least two IDE disk drives. Use of standard forty pin connectors and forty wire ribbon cable having certain pairs of wires uniquely twisted so as to allow the system to independently access the IDE drives.

Abstract: A computer system provides a RESET-signal for resetting registers upon start-up of the system, and includes a central processor unit (CPU) of an optional type and a detect circuit for determining which optional type. On start-up, the CPU sends out an initial memory reference at the highest possible address. The first type of CPU has a memory address register of N bits. The memory address register of the second type of CPU has a memory address register of N+M bits. The upper M bits input to the memory address register of the first type of CPU are grounded. A detect circuit is activated by the CPU addressing memory and receives at least one of the M upper bits. If that bit is not grounded, then the CPU is of the second type and, if grounded, it is of the first type. The RESET-signal upon start-up assures that the detect circuit will be activated on start-up.

Abstract: An electronic circuit for the detection of required operational speed of one or more integrated circuit semiconductor chips is used in conjunction with an off-the-shelf integrated circuit tester. The tester provides timing, control and a display. Each of the integrated circuit semiconductor chips is provided with a ring oscillator circuit for generating a series of pulses, timed by the tester for a fixed period of time. A counter, formed in each of the semiconductor chips counts the number of pulses generated during the fixed period of time. A number, generated in the tester, indicative of a required speed of operation is set in a latch assembly that is formed in each of the semiconductor chips. A comparator, also formed in each of the semiconductor chips, compares the contents of the latch with the contents of the counter and if the contents of the counter is equal to or larger than the contents of the latch, the tested semiconductor chip is acceptable. A display in the tester indicates the result.

Abstract: A cathode ray tube display device has conductive plates mounted adjacent the four sides of the CRT faceplate. These plates are positioned to sense electromagnetic noise radiation generated by the CRT. The plates are coupled to differential circuits so that normally the noise signals generated in the plates cancel. However when a finger or other object is placed at or near the CRT faceplate, the noise radiation field is disturbed, and the changed signals generated in the plates are sensed by the circuits to provide output signals indicative of the coordinate position of the object at the faceplate. The plates are preferably mounted in the front bezel of the display cabinet.