Abstract: A multi-core microprocessor supports a plurality of operating states that provide different levels of performance and power consumption to the microprocessor and its cores. A control unit puts selected cores into selected operating states at selected times. A core-specific synchronization register is provided for each core external to the core and readable by the control unit. Each core responds to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register. The control unit causes power saving actions that affect shared resources provided that the actions do not reduce performance of any core sharing the resources below the core's target operating state.

Abstract: A microprocessor includes one or more memories configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed. A method includes receiving from a memory a first N-bit wide microcode word, determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value, if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, and if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word.

Abstract: A microprocessor includes an instruction cache and a hardware state machine configured to detect a no operation (NOP) slide by counting a continuous sequence of NOP instructions within a stream of instructions fetched from the instruction cache. The microprocessor is configured to suspend execution of the stream of instructions, and transfer control to another routine, in response to detecting the NOP slide.

Abstract: A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.

Abstract: A microprocessor includes a plurality of processing cores each including a hardware instruction translator that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor. The microinstructions are encoded in a distinct manner from the manner in which the instructions of the x86 and ARM instruction sets are defined. Each core includes an execution pipeline that executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. Each core uses and associated indicator to determine whether it will boot as an x86 ISA core or an ARM ISA core when reset. The indicators are configurable to indicate that at least one of the cores will boot as an x86 ISA core and at least one other of the cores will boot as an ARM ISA core.

Abstract: A secure memory, key expansion logic, and decryption logic are provided for a microprocessor that executes encrypted instructions. The secure memory stores a plurality of decryption key primitives. The key expansion logic selects two or more decryption key primitives from the secure memory and then derives a decryption key from them. The decryption logic uses the decryption key to decrypt an encrypted instruction fetched from the instruction cache. The decryption key primitives are selected on the basis of an encrypted instruction address, one of them is rotated by an amount also determined by the encrypted instruction address, and then they are additively or subtractively accumulated, also on the basis of the encrypted instruction address.

Abstract: A microprocessor conditionally grants a request to switch from a normal execution mode in which encrypted instructions cannot be executed, into a secure execution mode (SEM). Thereafter, the microprocessor executes a plurality of instructions, including a store-key instruction to write a set of one or more cryptographic key values into a secure memory of the microprocessor. After fetching an encrypted program from an instruction cache, the microprocessor decrypts the encrypted program into plaintext instructions using decryption logic within the microprocessor's instruction-processing pipeline.

Abstract: A microprocessor is provided in which an encrypted program can replace the decryption keys that are used to decrypt sections of the encrypted program. The microprocessor may be decrypting and executing a first section of the encrypted program when it encounters, decrypts, and executes an encrypted store-key instruction to store a new set of decryption keys. After executing the store-key instruction, the microprocessor decrypts and executes a subsequent section of the encrypted program using the new set of decryption keys. On-the-fly key switching may occur numerous times with successive encrypted store-key instructions and successive sets of encrypted instructions.

Abstract: A microprocessor and method are provided for securely decrypting and executing encrypted instructions within a microprocessor. A plurality of master keys are stored in a secure memory. Encrypted instructions are fetched from an instruction cache. A set of one or more master keys are selected from the secure memory based upon an encrypted instruction fetch address. The selected set of master keys or a decryption key derived therefrom is used to decrypt the encrypted instructions fetched from the instruction cache. The decrypted instructions are then securely executed within the microprocessor. In one implementation, the master keys are intervolved with each other to produce a new decryption key with every fetch quantum. Moreover, a new set of master keys is selected with every new block of instructions.

Abstract: A compressing instruction queue for a microprocessor including a queue and redirect logic. The queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the queue without leaving unused storage locations and beginning at a first available storage location in the queue. The redirect logic performs redirection and compression to eliminate empty locations or holes in the queue and to reduce the number of write ports interfaced with each storage location of the queue.

Abstract: A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction.

Abstract: A processor includes translation-lookaside buffer (TLB) and a mapping module. The TLB includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear. The TLB also includes an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries. The mapping module generates the invalidation bit vector.

Abstract: An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction.

Abstract: A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.

Abstract: A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second storage to default values specified by the ARM ISA, initializes the third storage to predetermined values, and begins fetching instructions of a first ISA. The first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA. The microprocessor updates the third storage in response to the first ISA instructions. In response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor refrains from modifying the non-ISA-specific state stored in the third storage and begins fetching instructions of the second ISA.

Abstract: A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program and a plurality of hardware registers. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state; when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state.

Abstract: An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based on the second value. An instruction translator translates the instruction into one or more microinstructions. An execution pipeline executes the microinstructions generated by the instruction translator. The instruction translator, rather than the execution pipeline, generates the constant value for the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline.

Abstract: A processor includes a storage configured to receive a snapshot of a state of the processor prior to performing a set of computations in an approximating manner. The processor also includes an indicator that indicates an amount of error accumulated while the set of computations is performed in the approximating manner. When the processor detects that the amount of error accumulated has exceeded an error bound, the processor is configured to restore the state of the processor to the snapshot from the storage.

Abstract: A processor includes an indicator configured to indicate a first mode or a second mode and a functional unit configured to perform computations with a full degree of accuracy when the indicator indicates the first mode and to perform computations with less than the full degree of accuracy when the indicator indicates the second mode.

Abstract: A processor includes a decoder that decodes an instruction that instructs the processor to perform subsequent computations in an approximate manner and a functional unit that performs the subsequent computations in the approximate manner in response to the instruction. An instruction instructs the processor to clear an error amount associated with a value stored in a general purpose register of the processor. The error amount indicates an amount of error associated with a result of a computation performed by the processor in an approximate manner. The processor also clears the error amount in response to the instruction. Another instruction specifies a computation to be performed and includes a prefix that indicates the processor is to perform the computation in an approximate manner. The functional unit performs the computation specified by the instruction in the approximate manner specified by the prefix.