Patents by Inventor Terry R. Lee
Terry R. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120198201Abstract: A memory module is coupled to a number of controllers. The memory module is configured to configure each of a number of data input/output ports thereof as at least one of an input and an output in response to a first command from a particular controller of the controllers. The memory module is configured to partition itself into memory partitions in response to a second command from the particular controller so that each memory partition corresponds to a respective one of the controllers. Each of a number of data input/output ports of the controllers is configurable as at least one of an input and an output to correspond to a respective one of the input/output ports of the memory module. The first and second commands may originate from the particular controller, or the controllers may be coupled in parallel to the memory module.Type: ApplicationFiled: April 12, 2012Publication date: August 2, 2012Inventors: Terry R. LEE, David Ovard, Roy Greeff, Robert N. Leibowitz, Victor Tsai
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Patent number: 8234479Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.Type: GrantFiled: December 21, 2011Date of Patent: July 31, 2012Assignee: Round Rock Research, LLCInventors: Joseph M. Jeddeloh, Terry R. Lee
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Patent number: 8200884Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.Type: GrantFiled: June 20, 2011Date of Patent: June 12, 2012Assignee: Round Rock Research, LLCInventors: Terry R. Lee, Joseph M. Jeddeloh
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Patent number: 8181092Abstract: A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.Type: GrantFiled: December 15, 2006Date of Patent: May 15, 2012Assignee: Round Rock Research, LLCInventors: Terry R. Lee, Joseph M. Jeddeloh
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Patent number: 8171181Abstract: A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.Type: GrantFiled: May 5, 2008Date of Patent: May 1, 2012Assignee: Micron Technology, Inc.Inventors: Terry R. Lee, David Ovard, Roy Greeff, Robert N. Leibowitz, Victor Tsai
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Publication number: 20120089801Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.Type: ApplicationFiled: December 21, 2011Publication date: April 12, 2012Applicant: ROUND ROCK RESEARCH, LLCInventors: Joseph M. Jeddeloh, Terry R. Lee
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Patent number: 8127081Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.Type: GrantFiled: August 4, 2008Date of Patent: February 28, 2012Assignee: Round Rock Research, LLCInventors: Terry R. Lee, Joseph Jeddeloh
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Publication number: 20120036303Abstract: Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module.Type: ApplicationFiled: September 15, 2011Publication date: February 9, 2012Applicant: ROUND ROCK RESEARCH, LLCInventors: Terry R. Lee, Kevin J. Ryan
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Patent number: 8106520Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: GrantFiled: September 11, 2008Date of Patent: January 31, 2012Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Patent number: 8086815Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.Type: GrantFiled: March 14, 2011Date of Patent: December 27, 2011Assignee: Round Rock Research, LLCInventors: Joseph M. Jeddeloh, Terry R. Lee
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Patent number: 8040711Abstract: Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module. Thus, the system memory provides the advantages of “free space” optical connection in a compact arrangement of memory modules. In an alternate embodiment, the first memory module includes a beam splitter attached to the module substrate proximate the aperture. In another embodiment, the first and second memory modules are staged on the carrier substrate to provide an unobstructed path for optical signals.Type: GrantFiled: October 9, 2009Date of Patent: October 18, 2011Assignee: Round Rock Research, LLCInventors: Terry R. Lee, Kevin J. Ryan
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Patent number: 8035974Abstract: A system for supporting integrated circuit packages to prevent mechanical failure of the packages at their connection to a printed circuit board or card involves bracing the packages to the board or card, The packages may also be braced against one another. The structure is particularly well adapted to supporting vertical surface mount packages at a point spaced from the point where they connect to a printed circuit board or card.Type: GrantFiled: September 14, 1998Date of Patent: October 11, 2011Assignee: Round Rock Research, LLCInventors: David J. Corisis, Walter L. Moden, Terry R. Lee
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Publication number: 20110246743Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Applicant: ROUND ROCK RESEARCH, LLCInventors: Terry R. Lee, Joseph M. Jeddeloh
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METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING A MEMORY HUB ARCHITECTURE
Publication number: 20110167238Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.Type: ApplicationFiled: March 14, 2011Publication date: July 7, 2011Applicant: ROUND ROCK RESEARCH, LLCInventors: Joseph M. Jeddeloh, Terry R. Lee -
Publication number: 20110164446Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.Type: ApplicationFiled: March 14, 2011Publication date: July 7, 2011Applicant: Micron Technology, Inc.Inventors: Terry R. Lee, Joseph M. Jeddeloh
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Patent number: 7966444Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.Type: GrantFiled: October 15, 2010Date of Patent: June 21, 2011Assignee: Round Rock Research, LLCInventors: Terry R. Lee, Joseph M. Jeddeloh
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Publication number: 20110145453Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.Type: ApplicationFiled: February 2, 2011Publication date: June 16, 2011Applicant: ROUND ROCK RESEARCH, LLCInventors: Roy Greeff, Terry R. Lee
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Publication number: 20110101514Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradeable.Type: ApplicationFiled: January 12, 2011Publication date: May 5, 2011Inventors: Larry D. Kinsman, Jerry M. Brooks, Warren M. Farnworth, Walter L. Moden, Terry R. Lee
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Patent number: 7913005Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.Type: GrantFiled: November 3, 2008Date of Patent: March 22, 2011Assignee: Round Rock Research, LLCInventors: Roy Greeff, Terry R. Lee
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Patent number: 7911819Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.Type: GrantFiled: July 24, 2008Date of Patent: March 22, 2011Assignee: Micron Technology, Inc.Inventors: Terry R. Lee, Joseph M. Jeddeloh