Abstract: An AP allows a CTS generator provided within a control unit to generate a self-destined, e.g., IEEE802.11b standard-based CTS signal containing a duration time corresponding to each standard. Then, the AP notifies to each STA operated based on the 11b standard in a basic service set, that it is being ready for transmission due to the transmission of the CTS signal, thereby to prohibit the operation of the corresponding STA. Further, the AP transmits a beacon based on an IEEE802.11g standard to thereby set a condition based on this standard and is caused to perform transmission/reception to and from the corresponding STA alone over the duration time indicated by the 11b standard. In a reverse case, the AP transmits a CTS signal containing a self-destined duration time under the IEEE802.11g standard to prohibit the operation of the corresponding STA based on the 11g standard.

Abstract: A multicarrier wireless communication system is capable of switching the modulation scheme used by each carrier during communication. This communication system includes error detectors for detecting error bits separately for respective carriers by comparing the data block of each carrier before and after correction. The modulation scheme used by a particular carrier is switched to an appropriate modulation scheme, when the S/N ratio of the particular carrier is deteriorated or improved, on the basis of the information about the corrected error bits.

Abstract: A method of controlling a receiving operation includes, receiving a transmission frame into a wireless device, and decoding the transmission frame. A header information in the transmission frame is analyzed. Then, the receiving operation is suspended in response to the header information.

Abstract: A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for indicating independent data is supplied to the data computing unit. A data processing instruction signal for distinguishing a data processing instruction from other instructions is issued from an instruction decoder. The R/L register for distinguishing independent data is controlled by the data processing instruction signal. In the data computing unit, the portion related to storing independent data is multiplexed according to the number of independent data to be processed, and this multiplexed portion is controlled by the R/L select signal supplied from the control unit.

Abstract: A method for establishing a wireless connection between a first wireless device provided in a computer and a second wireless device, wherein group information that identifies the first wireless device is created and set for the first wireless device. The group information is transmitted to the second wireless device and is set for it. The first wireless device creates identification information that identifies the second wireless device with the group information to set it for the second wireless device. The first wireless device uses both of the group information and identification information to specify the second wireless device.

Abstract: An FFT operational device includes memory banks, an FFT operational circuit, and an FFT memory control circuit. The memory banks can overwrite pieces of data to specified address locations simultaneously or read out the data from the locations simultaneously. The operational circuit receives operands read out from the banks simultaneously to perform an FFT operation processing on the operands to output operation results simultaneously, and repeats the FFT operation processing a predetermined number of times. The memory control circuit receives the operation results output from the operational circuit simultaneously, and changes the order of the data in such a way that the pieces of data required for the operational circuit in the successive operation processing will be provided simultaneously. The resultant data are overwritten to the memory banks. The operational device thereby performs FFT or IFFT processing on hardware, the storage capacity thus being reduced with operational speed increased.

Abstract: A local timer includes a dividing counter which counts a first clock and outputs a reference counting signal divided from the first clock; a timing synchronizing timer which counts a timing synchronizing timer value in synchronization with a reference timer responsive to the reference counting signal; a first buffer which stores a counted value of the dividing counter in synchronization with a second clock, when operation is by the first clock; a second buffer which stores the timing synchronizing timer value in synchronization with the second clock, when operation is by the first clock; a first adder which adds a first or second offset value to the stored value in the first buffer in synchronization with the second clock, when the first clock is suspended; and a second adder which adds a set value to the timing synchronizing timer value responsive to a carry from the first adder.

Abstract: A computation circuit which can obtain n+m-digit accumulation results by using an n-digit computation unit. This computation circuit comprises a computation unit which performs additions of n-digit data; an m-digit up/down counter; and a control circuit which uses the up/down counter to generate the upper m digits of the computation result. In a preferred embodiment, the control circuit increments by one the up/down counter when carry-over occurs in the computation unit, and when the input data of the computation unit is negative, decrements by one the up/down counter. In another preferred embodiment, the control circuit increments or decrements by one the up/down counter when positive or negative overflow occurs in the computation unit, and decrements by one the up/down counter when the final computation result of the computation unit is negative or is a positive number greater than 2n?1?1.

Abstract: A loop control circuit and a loop control method that allow control on multiplexed loop operations to be executed with less overhead are provided. A loop control circuit comprises a means for address storage that stores in memory the address of a loop instruction at a second or subsequent stage in multiplexed loops or the address of the instruction immediately preceding the loop instruction when the loop instruction is executed for the first time, a means for loop instruction recurrence prediction that predicts a recurrence of the loop instruction at the second or subsequent stage by comparing the address of the loop instruction or the address of the instruction immediately preceding the loop instruction stored in memory with a value at a program counter and a means for loop instruction skipping that skips the loop instruction if it is predicted that the loop instruction is to occur next.

Abstract: An AP allows a CTS generator provided within a control unit to generate a self-destined, e.g., IEEE802.11b standard-based CTS signal containing a duration time corresponding to each standard. Then, the AP notifies to each STA operated based on the 11b standard in a basic service set, that it is being ready for transmission due to the transmission of the CTS signal, thereby to prohibit the operation of the corresponding STA. Further, the AP transmits a beacon based on an IEEE802.11g standard to thereby set a condition based on this standard and is caused to perform transmission/reception to and from the corresponding STA alone over the duration time indicated by the 11b standard. In a reverse case, the AP transmits a CTS signal containing a self-destined duration time under the IEEE802.11g standard to prohibit the operation of the corresponding STA based on the 11g standard.

Abstract: A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for indicating independent data is supplied to the data computing unit. A data processing instruction signal for distinguishing a data processing instruction from other instructions is issued from an instruction decoder. The R/L register for distinguishing independent data is controlled by the data processing instruction signal. In the data computing unit, the portion related to storing independent data is multiplexed according to the number of independent data to be processed, and this multiplexed portion is controlled by the R/L select signal supplied from the control unit.

Abstract: A method of controlling a receiving operation includes, receiving a transmission frame into a wireless device, and decoding the transmission frame. A header information in the transmission frame is analyzed. Then, the receiving operation is suspended in response to the header information.

Abstract: A local timer includes a first input circuit which has input thereto a first clock, a dividing counter which counts the clock and outputs a reference counting signal, wherein a frequency of the reference counting signal is divided from the first clock, a timing synchronizing timer which counts a timing synchronizing timer value in synchronization with a reference timer in an access point, in response to the reference counting signal, a second input circuit which has input thereto a second clock, wherein a frequency of the second clock is less than a frequency of the first clock, a first buffer which stores a counted value in the first counter in synchronization with the second clock, when the station is operated by the first clock, a second buffer which stores the timing synchronizing timer value in synchronization with the second clock, when the station is operated by the first clock, a first adder which adds a first offset value or a second offset value to the stored value in the first buffer in synchroniza

Abstract: A key expander expands a secret key used in a common-key cryptographic scheme into a sequence of working keys that are used in one order for encryption and in the reverse order for decryption. The key expander includes registers that store a number of initial working keys sufficient to start the key expansion process in one direction. Toward the end of a key expansion cycle in this direction, an equivalent number of final working keys are stored in further registers, for use as initial keys when the working key sequence is generated in the opposite direction. The key expander is then ready to start key expansion in either direction without delay.

Abstract: An arithmetic unit includes a memory, an arithmetic logic unit, a register and a combining circuit. The arithmetic logic unit executes a predetermined arithmetic operation with respect to the data read from memory. The register temporarily stores the data read from the memory. The combining circuit selects one of the arithmetic logic unit and the register. The combining circuit replaces a part of the data read from the memory with output data received from the selected one of the arithmetic logic unit and the register.

Abstract: A loop control circuit and a loop control method that allow control on multiplexed loop operations to be executed with less overhead are provided. A loop control circuit comprises a means for address storage that stores in memory the address of a loop instruction at a second or subsequent stage in multiplexed loops or the address of the instruction immediately preceding the loop instruction when the loop instruction is executed for the first time, a means for loop instruction recurrence prediction that predicts a recurrence of the loop instruction at the second or subsequent stage by comparing the address of the loop instruction or the address of the instruction immediately preceding the loop instruction stored in memory with a value at a program counter and a means for loop instruction skipping that skips the loop instruction if it is predicted that the loop instruction is to occur next.

Abstract: A computation circuit which can obtain n+m-digit accumulation results by using an n-digit computation unit. This computation circuit comprises a computation unit which performs additions of n-digit data; an m-digit up/down counter; and a control circuit which uses the up/down counter to generate the upper m digits of the computation result. In a preferred embodiment, the control circuit increments by one the up/down counter when carry-over occurs in the computation unit, and when the input data of the computation unit is negative, decrements by one the up/down counter. In another preferred embodiment, the control circuit increments or decrements by one the up/down counter when positive or negative overflow occurs in the computation unit, and decrements by one the up/down counter when the final computation result of the computation unit is negative or is a positive number greater than 2n−1−1.

Abstract: With this invention, operation testing can be performed using general operation and emulation operation. With the MPU of this invention, using emulation operation, commands for transferring data between register with scanning function 104 and register without scanning function 103 are input by scanning to command register with scanning function 101. Next, using general operation, the command execution is performed. Following this, the data of register 104 with scanning function is read. With this invention, it is possible to provide a semiconductor integrated circuit with a small circuit scale and with a short time required for operation testing.

Abstract: There is disclosed a compact arithmetic circuit for obtaining an absolute-valued distance (AVD) between two digital data. An inverter 11 generates the data * .beta. which is derived from the data .beta. as the 1's complement thereof. An ALU 12 adds the data .alpha. and the data * .beta. when a carry data C1 is inputted thereto. An inverter 13 generates a new carry data C2 from the add result of the ALU 12 and feeds it back to the ALU 12. Each bit of the add result by the ALU 12 is inverted by an inverter 15 and is given to a selector 14. After the initial add operation, the ALU 12 adds the data .alpha. and the data * .beta. by using carry data C2 as the input thereto. A selector 14 selects either the first add result by the ALU 12, the output data from the inverter 15 corresponding to the first add result, the second add result by the ALU 12, or the output data of the inverter 15 corresponding to the second add result, and outputs the selected as a correct AVD.