Abstract: Method and system for memory devices is provided. The system includes a plurality of non-volatile storage elements connected in a string between a source side element and a drain side element; a plurality of bit lines, wherein each bit line is connected to a plurality of non-volatile storage elements; and a plurality of word lines, the plurality of word lines include a dummy word line between a source side select element and a first word line that is connected to a first non-volatile storage element to be programmed, wherein a program voltage is applied to the first non-volatile storage element connected to the first word line and an intermediate voltage is applied to a second non-volatile storage element connected to the dummy word line.

Abstract: A process for reading data (including verifying during programming) from a selected non-volatile storage elements of a group (e.g., NAND string) of non-volatile storage elements includes maintaining an intermediate voltage as a control gate voltage for an unselected non-volatile storage element and subsequently changing the control gate voltage for the unselected non-volatile storage element from the intermediate voltage to a read enable voltage. The control gate voltage for the selected non-volatile storage element is raised from a standby voltage (which is different than the intermediate voltage) to a read compare voltage. While the control gate for the selected non-volatile storage element is at the read compare voltage and the control gate for the unselected non-volatile storage element is at the read enable voltage, the state of the selected non-volatile storage element is sensed to determine information about the data stored in the selected non-volatile storage element.

Abstract: A process for reading data (including verifying during programming) from a selected non-volatile storage elements of a group (e.g., NAND string) of non-volatile storage elements includes maintaining an intermediate voltage as a control gate voltage for an unselected non-volatile storage element and subsequently changing the control gate voltage for the unselected non-volatile storage element from the intermediate voltage to a read enable voltage. The control gate voltage for the selected non-volatile storage element is raised from a standby voltage (which is different than the intermediate voltage) to a read compare voltage. While the control gate for the selected non-volatile storage element is at the read compare voltage and the control gate for the unselected non-volatile storage element is at the read enable voltage, the state of the selected non-volatile storage element is sensed to determine information about the data stored in the selected non-volatile storage element.

Abstract: A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.

Abstract: A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.

Abstract: A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.

Abstract: A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.

Abstract: A nonvolatile register includes at least one memory cell. The memory cell has one word gate and first and second nonvolatile memory elements controlled by first and second control gates, respectively. Data is stored in one of the first and second nonvolatile memory elements, and the other of the first and second nonvolatile memory elements does not function as an element which stores data.

Abstract: A non-volatile semiconductor memory device enabling reading at high speed has a memory cell array including a plurality of memory cells arranged in a column direction and a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates. One of the first and second non-volatile memory elements stores data, but the other does not function as an element which stores data.

Abstract: A nonvolatile semiconductor storage device includes a memory cell array region in which a plurality of memory cells arranged in a row direction and a column direction, each of the memory cells having first and second MONOS memory cells and being controlled by one word gate and two control gates. The memory cell array region includes a plurality of sectors which are formed by dividing the memory cell array region in the row direction, and the longitudinal direction of the sectors is the column direction. Each of the plurality of sectors includes small blocks which are formed by dividing each of the sectors in the column direction. First to fourth control gate line drivers are arranged in each of local driver areas between which two adjacent small blocks are disposed. The first to fourth control gate drivers set the potentials of the first and second control gates within one corresponding small block, independently of the other small block.

Abstract: A non-volatile semiconductor device in which the number of redundant cells is not increased in proportion to the number of simultaneously accessed bits, having a redundant cell layout which prevents an increase in access time. This non-volatile semiconductor memory device has a regular cell array in which a plurality of memory cells are arranged. The regular cell array is divided into N sector regions in the row direction. Each of the N sector regions is divided into n first memory blocks in the row direction. One of the n first memory blocks is a redundant memory block. The (n?1) first memory blocks correspond to (n?1) input/output terminals.

Abstract: A non-volatile semiconductor memory device having a memory cell array region in which a plurality of memory cells, each having first and second MONOS memory cells controlled by a word gate and control gates, are arranged in first and second directions. The memory cell array region has a plurality of sector regions divided in the second direction. Each of a plurality of control gate drivers is capable of setting a potential of first and second control gates in the corresponding sector region independently of other sector regions. A plurality of switching elements which select connection/disconnection are formed at connections between a plurality of main bit lines and a plurality of sub bit lines.

Abstract: A non-volatile semiconductor memory device has a memory cell array region in which a plurality of memory cells are disposed in both column and row directions, each of the memory cells having first and second MONOS memory cells controlled by a word gate and first and second control gates. The memory cell array region is divided in the row direction into a plurality of sector regions extending longitudinally in the column direction. Each of the sector regions is divided into a plurality of large blocks, such as eight large blocks. There are eight control gate drivers for each sector region. Each of these eight control gate drivers sets potentials for first and second control gates of all the memory cells disposed within the corresponding one block of the eight large blocks.

Abstract: A voltage generation section, which generates voltages for driving the control gates in a plurality of nonvolatile memory cells, has a booster circuit and a voltage control circuit. The voltage control circuit has a plurality of voltage output terminals, and switches and outputs a plurality of voltages inputted from the booster circuit to a plurality of voltage output terminals in accordance with a selection state of the nonvolatile memory cell. The voltage control circuit pre-drives a control gate line by outputting a maximum voltage among the voltages to all of the voltage output terminals in a pre-drive period. A disconnection state, in which no voltage from the booster circuit is outputted, is set in a period prior to the pre-drive period, and a power supply voltage may be outputted instead of the voltage from the booster circuit.

Abstract: A non-volatile semiconductor memory device in which one I/O line is provided corresponding to one block region. 2N (four, for example) memory cells are provided in one block region. The adjacent memory cells are connected by a connect line. A bit line is connected to each connect line. Four bit lines are provided in one block region. The four bit lines in one block region are commonly connected to the I/O line through first select gates. A second select gate is provided between the bit line which is located at the boundary between the i-th and (i+1)th block regions which are adjacent to each other in a row direction and the I/O line corresponding to the i-th block region.

Abstract: A file storage type non-volatile semiconductor memory device suitable for simultaneously reading data from memory cells or programming data to memory cells, the number of bits of the data being greater than the number of I/O terminals, has a plurality of sector regions obtained by dividing a memory cell array region in a column direction. Each of the sector regions includes four main control gate lines extending in a row direction, a plurality of control gate driver sections which drive the main control gate lines, and a plurality of sub control gate lines extending in the column direction. Each of the sub control gate lines is connected in common with first and second control gates which are adjacent to each other in the row direction and belonged to different two of the memory cells which are adjacent to each other in the row direction. The sub control gate lines are sequentially connected to one of the four main control gate lines in the row direction.

Abstract: A nonvolatile semiconductor memory device prevents the voltage from dropping in a voltage raising circuit at the switching time of a control gate voltage at an address changing time. This nonvolatile semiconductor memory device has a voltage generation section which generates voltages for driving the control gates in a plurality of nonvolatile memory cells. The voltage generation section has the voltage raising circuit and a voltage control circuit. The voltage control circuit has a plurality of voltage input terminals and a plurality of voltage output terminals, and switches and outputs a plurality of voltages inputted from the voltage raising circuit through the voltage input terminals to the voltage output terminals in accordance with a selection state of then on volatile memory cells.

Abstract: A nonvolatile semiconductor storage device includes a memory cell array region in which a plurality of memory cells are arranged, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates. In reading out data from one of the first and second nonvolatile memory elements of the memory cell, a control voltage of a control-gate-line selection switching element connected to a sub control gate line to which an override voltage is applied, is greater than that of a control-gate-line selection switching element connected to a sub control gate line to which a read voltage is applied.

Abstract: When data is read from one of the memory elements in a memory cell [i] in a reverse read mode, a word line WL1 is set at a supply voltage Vdd, a control gate CG [i+1] is set at 1.5V, and a control gate CG [i] is set at an override voltage (for example, 3V). When a bit line BL [I+1] is 0V and a bit line BL [i] is connected to a sense amplifier, the gate voltage BS0 of a bit line selection transistor located midway of the bit line BL [i] is set at a high voltage (for example, 4.5V), in order to ensure current which flows through the bit line BL [i] connected to the drain of the memory cell [i].

Abstract: A nonvolatile semiconductor memory device which reduces the characteristic difference depending on the cell position, occurring between a cell current from a regular memory cell and a reference cell current, has a regular cell array and a reference cell array. The regular cell array has M numbers of large blocks formed by dividing the regular cell array in a column direction. Each of the M numbers of large blocks has m numbers of small blocks formed by finely dividing each of the large blocks in the column direction. The number and arrangement of the reference memory cells within the reference cell array is coincident with the number and arrangement of the memory cells arranged in the small block as a minimum unit for cell-array manufacture process.