Patents by Inventor Teruhiro KUWAJIMA

Teruhiro KUWAJIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170148732
    Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate and including a plurality of wiring layers, and a first coil, a second coil, and a third coil which are formed above the semiconductor substrate. In a region located under the first coil and overlapping the first coil in plan view, the second and third coils CL2a and CL2b are disposed. The second and third coils are foamed in the same layer and electrically coupled in series to each other. Each of the second and third coils and the first coil are not coupled to each other via a conductor, but are magnetically coupled to each other.
    Type: Application
    Filed: October 25, 2016
    Publication date: May 25, 2017
    Inventor: Teruhiro KUWAJIMA
  • Publication number: 20170062332
    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
    Type: Application
    Filed: June 20, 2016
    Publication date: March 2, 2017
    Inventors: Teruhiro KUWAJIMA, Akira MATSUMOTO, Yasutaka NAKASHIBA, Takashi IWADARE
  • Patent number: 9553042
    Abstract: A wiring structure thereof includes a first interlayer insulating film, a first wiring and a first electrode for the capacitive element embedded in the first interlayer insulating film, a barrier insulating film formed over the first interlayer insulating film to cover the wiring and the electrode, a second interlayer insulating film formed over the barrier insulating film, and a second wiring and a second electrode for the capacitive element embedded in the second interlayer insulating film. The lower surface of the second wiring is positioned in the middle of the thickness of the second interlayer layer film, and the lower surface of the second electrode is in contact with the barrier insulating film. The barrier insulating film of a portion interposed between both electrodes functions as a capacitance insulating film of the capacitive element and is thicker than the barrier insulating film of a portion covering the first wiring.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Teruhiro Kuwajima
  • Publication number: 20160056070
    Abstract: Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring.
    Type: Application
    Filed: November 3, 2015
    Publication date: February 25, 2016
    Inventor: Teruhiro KUWAJIMA
  • Publication number: 20160056107
    Abstract: A wiring structure thereof includes a first interlayer insulating film, a first wiring and a first electrode for the capacitive element embedded in the first interlayer insulating film, a barrier insulating film formed over the first interlayer insulating film to cover the wiring and the electrode, a second interlayer insulating film formed over the barrier insulating film, and a second wiring and a second electrode for the capacitive element embedded in the second interlayer insulating film. The lower surface of the second wiring is positioned in the middle of the thickness of the second interlayer layer film, and the lower surface of the second electrode is in contact with the barrier insulating film. The barrier insulating film of a portion interposed between both electrodes functions as a capacitance insulating film of the capacitive element and is thicker than the barrier insulating film of a portion covering the first wiring.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 25, 2016
    Inventor: Teruhiro KUWAJIMA
  • Patent number: 9209123
    Abstract: Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: December 8, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Teruhiro Kuwajima
  • Publication number: 20150108655
    Abstract: Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 23, 2015
    Inventor: Teruhiro KUWAJIMA