Patents by Inventor Teruhisa Ichise
Teruhisa Ichise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9275956Abstract: A semiconductor substrate includes scribe and product regions, with grooves formed in the scribe region. The grooves are embedded with an insulating film to provide an isolation region, and an active region, including semiconductor elements, is formed in the product region. Dummy patterns are formed in the scribe region, which include a first dummy pattern and second dummy patterns for preventing dishing of the insulating film. The second dummy patterns are surrounded and defined by the isolation region. A target pattern for optical pattern recognition is arranged over the first dummy pattern, and includes a first conductive film. A plane area of the first dummy pattern is larger than a plane area of each of the second dummy patterns, and the first dummy pattern and the second dummy patterns are arranged in order from an edge of the semiconductor substrate toward the product region.Type: GrantFiled: June 15, 2015Date of Patent: March 1, 2016Assignee: Renesas Electronics CorporationInventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Publication number: 20150279788Abstract: A semiconductor substrate includes scribe and product regions, with grooves formed in the scribe region. The grooves are embedded with an insulating film to provide an isolation region, and an active region, including semiconductor elements, is formed in the product region. Dummy patterns are formed in the scribe region, which include a first dummy pattern and second dummy patterns for preventing dishing of the insulating film. The second dummy patterns are surrounded and defined by the isolation region. A target pattern for optical pattern recognition is arranged over the first dummy pattern, and includes a first conductive film. A plane area of the first dummy pattern is larger than a plane area of each of the second dummy patterns, and the first dummy pattern and the second dummy patterns are arranged in order from an edge of the semiconductor substrate toward the product region.Type: ApplicationFiled: June 15, 2015Publication date: October 1, 2015Inventors: Hiroyuki UCHIYAMA, Hiraku CHAKIHARA, Teruhisa ICHISE, Michimoto KAMINAGA
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Patent number: 9059100Abstract: A method of forming a semiconductor IC includes forming grooves in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: GrantFiled: October 22, 2013Date of Patent: June 16, 2015Assignee: Renesas Electronics CorporationInventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Publication number: 20140045320Abstract: A method of forming a semiconductor IC includes forming grooves in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: ApplicationFiled: October 22, 2013Publication date: February 13, 2014Applicant: Renesas Electronics CorporationInventors: Hiroyuki UCHIYAMA, Hiraku CHAKIHARA, Teruhisa ICHISE, Michimoto KAMINAGA
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Patent number: 8569107Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: GrantFiled: May 9, 2012Date of Patent: October 29, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Patent number: 8558352Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: GrantFiled: December 23, 2011Date of Patent: October 15, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Publication number: 20120220104Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: ApplicationFiled: May 9, 2012Publication date: August 30, 2012Inventors: Hiroyuki UCHIYAMA, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Patent number: 8183091Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: GrantFiled: April 9, 2010Date of Patent: May 22, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Publication number: 20120091565Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: ApplicationFiled: December 23, 2011Publication date: April 19, 2012Inventors: Hiroyuki UCHIYAMA, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Publication number: 20100197105Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: ApplicationFiled: April 9, 2010Publication date: August 5, 2010Inventors: Hiroyuki UCHIYAMA, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Patent number: 7696608Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: GrantFiled: November 30, 2007Date of Patent: April 13, 2010Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Technology Corp.Inventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Patent number: 7687849Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: May 29, 2008Date of Patent: March 30, 2010Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20090267160Abstract: A semiconductor device comprises an anti-fuse element. The anti-fuse element includes a semiconductor substrate, a first gate insulating film, a first gate electrode, a high-concentration impurity region formed in the semiconductor substrate under the first gate electrode, and first source/drain regions provided in the semiconductor substrate on both sides of the high-concentration impurity region. The first source/drain regions contain an impurity having the same conduction type as conduction type of the high-concentration impurity region.Type: ApplicationFiled: April 22, 2009Publication date: October 29, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Teruhisa ICHISE
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Publication number: 20080283970Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.Type: ApplicationFiled: November 30, 2007Publication date: November 20, 2008Inventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Publication number: 20080237752Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: May 29, 2008Publication date: October 2, 2008Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7417291Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: April 18, 2007Date of Patent: August 26, 2008Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7327014Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.Type: GrantFiled: November 21, 2006Date of Patent: February 5, 2008Assignee: Renesas Technology Corp.Inventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga
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Publication number: 20070187783Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: April 18, 2007Publication date: August 16, 2007Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7224034Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: November 2, 2004Date of Patent: May 29, 2007Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20070063315Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.Type: ApplicationFiled: November 21, 2006Publication date: March 22, 2007Inventors: Hiroyuki Uchiyama, Hiraku Chakihara, Teruhisa Ichise, Michimoto Kaminaga