Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: In order to prevent dusting from a peripheral end portion of a wafer, a semiconductor film formed is removed from at least the entire surface of the backside of the wafer and from the peripheral portion of the wafer by etching at a high etching rate relative to an insulating film present beneath the semiconductor film, to realize a semiconductor apparatus in which the semiconductor film is formed in an integrated circuit pattern region on the face side of the wafer. Thus, the problem of dusting from the peripheral portion of the wafer is obviated, and a semiconductor apparatus with high reliability is realized.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.

Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.

Abstract: In order to prevent dusting from a peripheral end portion of a wafer, a semiconductor film formed is removed from at least the entire surface of the backside of the wafer and from the peripheral portion of the wafer by etching at a high etching rate relative to an insulating film present beneath the semiconductor film, to realize a semiconductor apparatus in which the semiconductor film is formed in an integrated circuit pattern region on the face side of the wafer.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.

Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.