Abstract: In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P+-type source region (8), an N-type body region (4) and an N+-body contact diffusion region (10) are surrounded by a P+-type drain region (9) and a P-type drift region (5). A gate electrode (7) is formed to overlap the end portion of the N-type body region (4). The end portion of the N-type body region (4) has a portion in which the gate electrode (7) and the P+-type source region (8) are not adjacent to each other.

Abstract: A high withstand voltage lateral semiconductor device capable of improving its on-state breakdown voltage and safe operation area (SOA) without lowering its current capabilities, and structured so as to be easy to produce.

Abstract: In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P+-type source region (8), an N-type body region (4) and an N+-body contact diffusion region (10) are surrounded by a P+-type drain region (9) and a P-type drift region (5). A gate electrode (7) is formed to overlap the end portion of the N-type body region (4). The end portion of the N-type body region (4) has a portion in which the gate electrode (7) and the P+-type source region (8) are not adjacent to each other.

Abstract: A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.

Abstract: An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different types of channel conductivity.

Abstract: A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.

Abstract: Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the second conduction type formed on a surface of the semiconductor substrate under the bonding pad. Characteristics do not deteriorate even when a breakdown occurs during wire bonding.

Abstract: A high withstand voltage lateral semiconductor device capable of improving its on-state breakdown voltage and safe operation area (SOA) without lowering its current capabilities, and structured so as to be easy to produce.

Abstract: A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.

Abstract: A high-voltage semiconductor device includes: a semiconductor region; a doped contact region; an isolating region; a metal electrode which is electrically connected with the doped contact region; and floating plate electrodes. A section of the metal electrode is extended onto an interlayer dielectric film and located over the respective plate electrodes. The extended section is capacitively coupled to the plate electrodes, respectively. A CMOS circuit, a resistor, a capacitor are formed in a portion of the semiconductor region which is surrounded with the doped contact region.

Abstract: An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate 1; a semiconductor layer 3 having a P? type active region 3a that is formed on the supporting substrate 1, interposing a buried oxide film 2 between the semiconductor layer 3 and the supporting substrate 1; and a gate electrode 16a that is formed on the semiconductor layer 103, interposing a gate oxide film 17 and a part of a LOCOS film 5a between the gate electrode 16a and the semiconductor layer 103, wherein the P? type active region 3a has: an N+ type source region 11; a P type body region 12; a P+ type back gate contact region 14; an N type drain offset region 19; an N+ type drain contact region 20; and an N type drain buffer region 18 that is formed in a limited region between the N type drain offset region 19 and the P type body region 12, an

Abstract: A high-voltage semiconductor device includes: a drain region; a metal electrode electrically connected to the drain region; and electrically floating plate electrodes formed on a field insulating film over a semiconductor regionm. Parts of the metal electrodes are extended onto the interlevel dielectric film and located over the respective plate electrodes. Each part of the metal electrode is capacitively coupled to associated one of the plate electrodes.

Abstract: A high-voltage semiconductor device includes: a semiconductor region; a doped contact region; an isolating region; a metal electrode which is electrically connected with the doped contact region; and floating plate electrodes. A section of the metal electrode is extended onto an interlayer dielectric film and located over the respective plate electrodes. The extended section is capacitively coupled to the plate electrodes, respectively. A CMOS circuit, a resistor, a capacitor are formed in a portion of the semiconductor region which is surrounded with the doped contact region.

Abstract: A high-voltage semiconductor device includes: a drain region; a metal electrode electrically connected to the drain region; and electrically floating plate electrodes formed on a field insulating film over a semiconductor region. Parts of the metal electrodes are extended onto the interlevel dielectric film and located over the respective plate electrodes. Each part of the metal electrode is capacitively coupled to associated one of the plate electrodes.