Abstract: An electronic circuit apparatus and integrated circuit device, wherein an arrangement of connection terminals, external connection terminals and input/output interface circuits of a semiconductor chip as a unit circuit device is optimized so as to attain suppression of a power consumption and a shorter signal transmission time, configured that only connection pads are allocated to be arranged on a mutually adjacent side of semiconductor chips 1 and 2, and input/output interface circuits, test pads and external connection pads are arranged along remaining three sides, moreover, the connection pads and the electronic circuits are directly connected not via the input/output interface circuits.

Abstract: A method of manufacturing the semiconductor chips comprises the steps of: pasting on a substrate an adhesive sheet having a property to retain its adhesive strength prior to a processing, then lose its adhesive strength after the processing; fixing a plurality of non-defective bare chips on this adhesive sheet, with their Al electrode pad surfaces facing down; coating a resin on a whole area other than the Al electrode pad surfaces of the plurality of non-defective bare chips including interspaces therebetween; applying a predetermined process to the adhesive sheet to weaken its adhesive strength of the adhesive sheet; peeling off a pseudo wafer bonding non-defective bare chips; and dicing the plurality of non-defective bare chips into a discrete non-defective electronic part by cutting the pseudo wafer at a position of the resin between respective non-defective bare chips.

Abstract: A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) are formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of a of recesses (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).

Abstract: A method of manufacturing the semiconductor chips comprises the steps of: pasting on a substrate an adhesive sheet having a property to retain its adhesive strength prior to a processing, then lose its adhesive strength after the processing; fixing a plurality of non-defective bare chips on this adhesive sheet, with their Al electrode pad surfaces facing down; coating a resin on a whole area other than the Al electrode pad surfaces of the plurality of non-defective bare chips including interspaces therebetween; applying a predetermined process to the adhesive sheet to weaken its adhesive strength of the adhesive sheet; peeling off a pseudo wafer bonding non-defective bare chips; and dicing the plurality of non-defective bare chips into a discrete non-defective electronic part by cutting the pseudo wafer at a position of the resin between respective non-defective bare chips.

Abstract: A semiconductor device of MCM type allowing high-density assembly and a process of fabricating the same is provided.

Abstract: A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) is formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of recess (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).

Abstract: A static random access memory device (SRAM) keeping a resistance value of a resistance element at a predetermined level regardless a process variation, by improving a special margin of a diffusion layer region at which the resistance element is formed and a node for connecting a gate electrode thereto. In the SRAM, there is provided a diffusion layer region in a substrate, having a first part of which may form a the resistance element, a second part of which is connected to the drain or source of the MIS access transistor, and a third part of which is connected to the source or drain of the MIS driver transistor and is defined the node, and there is provided an electrode layer connecting the gate of the MIS driver transistor and the node in the diffusion layer region.

Abstract: A static random access memory device (SRAM) keeping a resistance value of a resistance element at a predetermined level regardless a process variation, by improving a special margin of a diffusion layer region at which the resistance element is formed and a node for connecting a gate electrode thereto. In the SRAM, there is provided a diffusion layer region in a substrate, having a first part of which may form a the resistance element, a second part of which is connected to the drain or source of the MIS access transistor, and a third part of which is connected to the source or drain of the MIS driver transistor and is defined the node, and there is provided an electrode layer connecting the gate of the MIS driver transistor and the node in the diffusion layer region.

Abstract: In a static random access memory (SRAM), a memory cell ratio is increased without deteriorating an integration degree of this SRAM. The static random access memory is arranged by: trenches formed in a semiconductor substrate and an insulating layer for isolating elements within a memory cell forming region; one pair of word transistors; one pair of driver transistors for constituting a flip-flop by forming channel regions of the driver transistors in side surfaces of the trenches and by cross-connecting gate electrodes thereof and drain electrodes thereof at one pair of input/output terminals of the flip-flop; and one pair of word transistors connected between the one pair of input/output terminals of the flip-flop and a bit line.

Abstract: A multilayer interconnect structure for a semiconductor device. The structure comprises a lower patterned metallization layer, a higher patterned metallization layer, and filled holes for electrically interconnecting these two layers. The two metallization layers are formed out of aluminum or an aluminum alloy by high-temperature aluminum sputtering or aluminum reflow techniques. A suction-preventing layer is formed either at the bottoms of the contact holes or on the surface of the lower metallization layer to prevent the material of the lower metallization layer from being sucked into the overlying contact holes.

Abstract: A method for preparing an improved catalyst for use in the preparation of chlorine by the oxidization of hydrogen chloride with an oxygen-containing gas. The catalyst mainly comprises chromium oxide and can be used for a long period of time particularly under low oxygen content conditions, and the activity of the catalyst does not easily deteriorate, and in other words, the catalyst has a long life. Furthermore, there are disclosed the catalyst obtained by this preparation method, and a method for preparing chlorine from hydrogen chloride by the use of the catalyst. The method for preparing the improved catalyst comprises adding copper, an alkali metal and a rare earth metal, or adding chromium, copper, an alkali metal and a rare earth metal to a catalyst containing chromium oxide as a main component, and then calcining the catalyst at a temperature of 800.degree. C. or less.

Abstract: Disclosed herein is a process comprising introducing a chlorine-containing gas through an adsorbent to adsorb chlorine and thereafter reducing the pressure of the adsorbent to a pressure lower than that during the introduction, thereby obtaining an effluent gas with a higher chlorine concentration than that of the introduced gas. Among preferably usable adsorbents are zeolite, non-zeolite-type porous acidic oxides and active carbon.

Abstract: In a semiconductor memory serving as an SRAM mounted on a CMOS gate array, a memory cell is constituted by a pair of transistors of a first conductivity type channel and a pair of transistors of a second conductivity type channel of the CMOS gate array and load resistances formed on the gate electrodes of the pair of transistors of the first conductivity type channel. Although the CMOS gate array is used, a memory cell area is small and a large capacity can be easily obtained.

Abstract: Disclosed herein is a method for the stabilizing treatment of a catalyst comprising washing the catalyst with hot washing water following the preparation of the catalyst, the catalyst being composed principally of chromium oxide and used in the production of chlorine by the oxidation of hydrogen chloride with an oxygen-containing gas, thereby improving its catalytic activity and prolonging its life.