Abstract: An embodiment is a phase adjustment circuit includes a sine wave output circuit, a first multiplier, a second multiplier, and an adder. The sine wave output circuit is configured to output two sine wave signals of a fixed phase difference. The first multiplier is configured to multiply an amplitude of a first sine wave signal output from the sine wave output circuit by a first variable to generate a first output signal. The second multiplier is configured to multiply an amplitude of a second sine wave signal output from the sine wave output circuit by a second variable to generate a second output signal. The adder is configured to add the first output signal from the first multiplier and the second output signal from the second multiplier.

Abstract: A mixer includes a transistor to which an IF signal of ae positive phase side is input, a transistor to which an IF signal of a negative phase side is input, a transistor to which an LO signal is input, and a synthesizer which synthesizes components of a RF frequency band output from the drain terminals of the transistors in a negative phase, and synthesizes components of an IF frequency band output from the drain terminals of the transistors in the same phase.

Abstract: A phase adjustment circuit includes a clock generation circuit for generating a sine wave shaped clock signal, an amplifier circuit for amplifying the clock signal, a transmission line in which an input end is connected to an output terminal of the amplifier circuit, a load circuit which is connected to a termination of the transmission line and whose impedance can be adjusted from the outside, and an amplifier circuit in which a signal obtained by adding an output signal of the amplifier circuit and a return signal from the transmission line at an output terminal of the amplifier circuit is input.

Abstract: A single-phase differential conversion circuit of the present invention is provided with a differential amplifier including a positive-phase circuit for processing a positive-phase signal and a negative-phase circuit for processing a negative-phase signal; and a transmission line connected to an output terminal of the positive-phase circuit, wherein the transmission line rotates a phase of the positive-phase signal and reduces an intensity of the positive-phase signal. The other differential amplifier may be connected to a subsequent stage of the differential amplifier.

Abstract: The mixer circuit includes a mixer, an LO matching circuit inserted between an LO signal terminal and a first terminal of the mixer, an IF matching circuit inserted between the IF signal terminal and a second terminal of the mixer, and an RF matching circuit inserted between an RF signal terminal and a third terminal of the mixer. In the RF matching circuit, a reflection characteristic is set such that a minimum value of reflection loss appears on a high-frequency side of the frequency of the LO signal.

Abstract: A package includes a bottomed cylindrical container having an open upper surface, the container being made of a metal. An engaging section is provided by a step formed on an opening edge of the container and extending toward an outer peripheral side. A dielectric substrate is disposed on a bottom surface of the container, the dielectric substrate on which a device is mounted. An input/output interface is provided on a side surface of the container and connected to the device. A plate-like radio wave absorber is engaged to the engaging section so as to cover a whole region of the bottom surface of the container. A lid made of a metal closes an opening end of the container and seals the inside of the container.

Abstract: An embodiment is a radio communication transceiver including a first frequency multiplier configured to multiply a frequency of a local oscillator (LO) signal, a mixer configured to mix the LO signal and an intermediate frequency (IF) signal output from the first frequency multiplier to generate a radio frequency (RF) signal, a cancel signal generator configured to generate a cancel signal to cancel LO leakage generated in the mixer, an antenna configured to transmit an RF signal, and a multiplexer configured to output a signal obtained by adding the output signal of the mixer and the cancel signal to the antenna, where the cancel signal generator generates the cancel signal having a same absolute value of strength and an opposite phase at a same frequency with respect to the LO leakage generated in the mixer and input to the multiplexer.

Abstract: A DC block structure includes a dielectric (1), transmission lines (2a, 2b) having characteristic impedance of 50? and formed on a surface of the dielectric (1), transmission lines (3a, 3b) formed on the surface of the dielectric (1) so as to be connected with the transmission lines (2a, 2b) and designed so that characteristic impedance is higher than the characteristic impedance of the transmission lines (2a, 2b), and a capacitor (4) mounted on the transmission lines (3a, 3b) so as to connect the transmission line (3a) and the transmission line (3b) in series.

Abstract: An embodiment is a distributed amplifier including amplifier blocks, each of the amplifier blocks including a first transmission line to receive input of a signal to an input end, a second transmission line to output a signal from an output end, a first termination resistor having a first end connected to a terminal end of the first transmission line, a second termination resistor having a first end connected to an input end of the second transmission line, and unit cells arranged along the first and second transmission lines, each of the unit cells having an input terminal connected to the first transmission line and an output terminal connected to the second transmission line, the amplifier blocks are connected in cascade such that a terminal end of the second transmission line of one of the amplifier blocks is connected to the first transmission line of a subsequent amplifier block.

Abstract: In some embodiments, the phase adjustment circuit includes a clock generator that is configured to generate a sinusoidal clock signal, and may include a variable amplifier that is configured to receive the clock signal output from the clock generator as an input, output an amplitude-adjusted sinusoidal differential clock signal, and output an amplitude-adjusted in-phase signal. The phase adjustment circuit may include an adder that is configured to output a differential signal obtained by adding the in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier, a differential transmission line that includes two transmission lines configured to transmit the differential signal output from the adder, and a terminal circuit that is configured to terminate the differential transmission line where a signal is output from a terminal of any one of the two transmission lines.

Abstract: An embodiment is a phase adjustment circuit includes a sine wave output circuit, a first multiplier, a second multiplier, and an adder. The sine wave output circuit is configured to output two sine wave signals of a fixed phase difference. The first multiplier is configured to multiply an amplitude of a first sine wave signal output from the sine wave output circuit by a first variable to generate a first output signal. The second multiplier is configured to multiply an amplitude of a second sine wave signal output from the sine wave output circuit by a second variable to generate a second output signal. The adder is configured to add the first output signal from the first multiplier and the second output signal from the second multiplier.

Abstract: A mixer includes a transistor to which an IF signal of ae positive phase side is input, a transistor to which an IF signal of a negative phase side is input, a transistor to which an LO signal is input, and a synthesizer which synthesizes components of a RF frequency band output from the drain terminals of the transistors in a negative phase, and synthesizes components of an IF frequency band output from the drain terminals of the transistors in the same phase.

Abstract: A multiplexer includes an impedance converter. The impedance converter includes: a transmission line having a length of ?/4 (? is an in-transmission-line wavelength of a signal) and a characteristic impedance of 35?; and a transmission line having a length of ?/4 and a characteristic impedance of 70?. The impedance converter includes: a transmission line having a length of ?/4 and a characteristic impedance of 35?; and a transmission line having a length of ?/4 and a characteristic impedance of 70?.

Abstract: An embodiment includes an output circuit with transistors and a withstand voltage protection circuit. The withstand voltage protection circuit includes resistors connected between an output signal terminal on the positive phase side and an output signal terminal on the negative phase side. A switch includes an NMOS transistor having a gate terminal connected to the connection point of the resistors, a drain terminal connected to the bias voltage, and a source terminal connected to the base terminal of the transistor.

Abstract: In some implementations, the device may include a clock generator configured to generate a sinusoidal clock signal. The device may include a delay circuit configured to delay a signal output from the clock generator. The device may also include a first multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the clock generator by a first constant. Additionally, the device may include a second multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the delay circuit by a second constant. Also, the device may include an adder configured to add the signal output from the first multiplier and the signal output from the second multiplier.

Abstract: The mixer circuit includes a mixer, an LO matching circuit inserted between an LO signal terminal and a first terminal of the mixer, an IF matching circuit inserted between the IF signal terminal and a second terminal of the mixer, and an RF matching circuit inserted between an RF signal terminal and a third terminal of the mixer. In the RF matching circuit, a reflection characteristic is set such that a minimum value of reflection loss appears on a high-frequency side of the frequency of the LO signal.

Abstract: The driver circuit includes DC cut capacitors, an input buffer, input termination resistors connected in series between differential input signal terminals and an ESD protection circuit connected to a connection point of the input terminal resistors. The ESD protection circuit includes diodes.

Abstract: A phase adjustment circuit includes a clock generation unit (1) which generates a sinusoidal differential clock signal; a variable amplifier (2) which receives a differential clock signal output from the clock generation unit (1) as an input, outputs an amplitude-adjusted differential clock signal, and simultaneously outputs an amplitude-adjusted in-phase signal; an adding unit (3) which adds an in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier (2); a differential transmission line (4) which transmits the differential signal output from the adding unit (3); and a terminal circuit (5) which terminates the differential transmission line (4).

Abstract: Each unit cell (4a-1 to 4a-N) of the distributed double balanced mixer outputs a signal (R++) obtained by multiplexing the LO signal (LO+) on the positive phase side and the IF signal (IF+) on the positive phase side, a signal (RF??) obtained by multiplexing the LO signal (LO?) on the negative phase side and the IF signal (IF?) on the negative phase side, a signal (RF?+) obtained by multiplexing the LO signal (LO?) on the negative phase side and the IF signal (IF+) on the positive phase side, and a signal (RF+?) obtained by multiplexing LO signal (LO+) on the positive phase side and IF signal (IF?) on the negative phase side, to transmission lines (CPW20pp, CPW20nn, CPW20np, CPW20pn), without synthesizing the signals.

Abstract: A distributed amplifier includes: a transmission line having an input end that an input signal is input to; a transmission line having an output end that an output signal is output from; an input termination resistor connected to an end terminal of the transmission line; a plurality of unit cells arranged along the transmission lines, and having input terminals connected to the transmission line and output terminals connected to the transmission line; and a variable current source having one end connected to the end terminal of the transmission line and another end connected to a power supply voltage, and capable of adjusting a current amount between the transmission line and the power supply voltage.