Abstract: A digital signal process unit includes a first cancel signal generation unit and a second cancel signal generation unit. The first cancel signal generation unit generates, as a first cancel signal component, a cancel signal component corresponding to an image signal included in an analog signal output from a mixer. The second cancel signal generation unit generates, as a second cancel signal component, a cancel signal component corresponding to a leakage signal generated between an input and output of the mixer. The digital signal process unit includes subtractors for subtracting the first cancel signal component and the second cancel signal component from a signal component corresponding to a frequency band divided from an input signal to obtain a digital signal.

Abstract: A first phase adjuster adjusts the phase of any one of first and second AC voltages generated in a negative resistance circuit so that a shift amount ? in a first variable phase shifter falls within a range of 0 degrees??<180 degrees, and outputs the phase-adjusted AC voltage to the first variable phase shifter, and a second phase adjuster adjusts the phase of the other one of the first and second AC voltages generated in the negative resistance circuit so that a shift amount ? in a second variable phase shifter falls within a range of 0 degrees??<180 degrees, and outputs the phase-adjusted AC voltage to the second variable phase shifter.

Abstract: A wide-band analog input signal is converted into a digital output signal on the basis of a band division method without the need for filter circuits. An analog processing block Aj (j=2 to N, where N is an integer) down-converts an analog input signal Sx using a cutoff frequency fj-1 of a channel CHj-1 and A/D-converts an analog signal Saj acquired as a result. A digital processing block Bj doubles the signal strength of a first digital signal S1j acquired by Aj, subtracts a third digital signal S3j-1 of the channel CHj-1 from a second digital signal S2j acquired as a result, up-converts the acquired third digital signal S3j using the cutoff frequency fj-1, and outputs the result to an adder as a channel output signal Syj of a corresponding channel CHj.

Abstract: In an embodiment, an edge extraction method includes: emitting, toward an object, an electromagnetic wave polarized only in one direction perpendicular to a propagation direction; receiving a transmitted electromagnetic wave that has been transmitted through the object, using a receiving antenna; calculating an intensity in the propagation direction of the transmitted electromagnetic wave based on an intensity of the transmitted electromagnetic wave received by the receiving antenna; and obtaining a spatial distribution of the intensity in the propagation direction of the transmitted electromagnetic wave.

Abstract: A high frequency connection structure includes: a waveguide; a ridge coupler constituted by a conductor formed inside one end of the waveguide; a transmission line adjacent to the one end of the waveguide; an inductance adjustment structure which is provided between the ridge coupler and the transmission line and which adjusts ground inductance that is created due to a connection between the ridge coupler and the waveguide; and a wire which connects one end of the ridge coupler on a side of the transmission line and one end of the transmission line with each other.

Abstract: A linear amplifier includes a pre-amplifier configured to amplify an input differential signal, a post-amplifier configured to amplify an output signal of the pre-amplifier, an amplitude detector configured to detect an amplitude of an output signal of the post-amplifier, and an output voltage corresponding to the detected amplitude, a comparator configured to control a tail current source of the pre-amplifier such that when the output voltage of the amplitude detector is less than or equal to a reference voltage, a tail current of the pre-amplifier is set to a constant value, and when the output voltage of the amplitude detector is larger than the reference voltage, the tail current is reduced to make the output voltage of the amplitude detector equal to the reference voltage.

Abstract: A distributed amplifier includes a first transmission line for input, a second transmission line for output, an input termination resistor connecting a line end of the first transmission line and a power supply voltage, an output termination resistor connecting an input end of the second transmission line and a ground, unit cells having input terminals connected to the first transmission line and output terminals connected to the second transmission line, and a bias tee configured to supply a bias voltage to an input transistor of each of the unit cells. An emitter or source resistor of the input transistor of each of the unit cells is set to a different resistance value from each other in order for a collector or drain current flowing through the input transistor of each of the unit cells to have a uniform value.

Abstract: A negative capacitance circuit is connected between a drain and a source of the mixer transistor. With this configuration, the negative capacitance circuit is connected in parallel to a parasitic capacitance generated between the drain and the source of the mixer transistor, and the parasitic capacitance can be canceled out in a wide band by the negative capacitance circuit connected in parallel.

Abstract: A distributed mixer is configured of an artificial transmission line of which an input end is connected to an LO terminal and a terminal end is connected to an IF terminal, an artificial transmission line of which an input end is connected to an RF terminal, FETs that perform frequency synthesis of LO signals and RF signals and that are disposed following the artificial transmission lines and of which gates are connected to the artificial transmission line and sources are grounded, a bias circuit that applies gate bias voltage to a terminal end of the artificial transmission line, a terminating resistor that connects the terminal end of the artificial transmission line and a ground, and a plurality of transmission lines provided between the artificial transmission line and a drain of each FET.

Abstract: A linear amplifier includes a pre-amplifier configured to amplify an input differential signal, a post-amplifier configured to amplify an output signal of the pre-amplifier, an amplitude detector configured to detect an amplitude of an output signal of the post-amplifier, and an output voltage corresponding to the detected amplitude, a comparator configured to control a tail current source of the pre-amplifier such that when the output voltage of the amplitude detector is less than or equal to a reference voltage, a tail current of the pre-amplifier is set to a constant value, and when the output voltage of the amplitude detector is larger than the reference voltage, the tail current is reduced to make the output voltage of the amplitude detector equal to the reference voltage.

Abstract: A source injection mixer includes an FET, an IF matching circuit between an IF port and a gate of the FET, and that matches impedance of the IF port and impedance of the gate as viewed from the IF port, a shorting stub of which one end is connected to a source of the FET and another end is grounded, and shorter than ¼ of an electric length at a frequency of LO signals, an LO matching circuit between an LO port and the source of the FET, and that matches impedance of the LO port and impedance of the source as viewed from the LO port, and an RF matching circuit between an RF port and a drain of the FET, and that matches impedance of the RF port and impedance of the drain as viewed from the RF port.

Abstract: A wide-band analog input signal is converted into a digital output signal on the basis of a band division method without the need for filter circuits. An analog processing block Aj (j=2 to N, where N is an integer) down-converts an analog input signal Sx using a cutoff frequency fj-1 of a channel CHj-1 and A/D-converts an analog signal Saj acquired as a result. A digital processing block Bj doubles the signal strength of a first digital signal S1j acquired by Aj, subtracts a third digital signal S3j-1 of the channel CHj-1 from a second digital signal S2j acquired as a result, up-converts the acquired third digital signal S3j using the cutoff frequency fj-1, and outputs the result to an adder as a channel output signal Syj of a corresponding channel CHj.

Abstract: A resistive mixer includes a LO matching circuit inserted between the gate of an FET and a LO terminal, a bias circuit that is connected to the gate and applies a bias voltage to the gate, an RF matching circuit inserted between the drain of the FET and an RF terminal, and an IF matching circuit inserted between the drain and an IF terminal. The source of the FET is grounded. The impedance of the RF matching circuit seen from the drain of the FET at an IF frequency is open-circuit, and the impedance of the IF matching circuit seen from the drain of the FET at an RF frequency is open-circuit.

Abstract: In a distributed amplifier, a plurality of cascode amplifiers connected in parallel between an input side transmission line and an output side transmission line are provided, a transmission line is connected to an input terminal of an output transistor of each of the amplifiers, and a bias potential is applied from a bias circuit to the input terminal of the output transistor via the transmission line.

Abstract: A digital signal process unit includes a first cancel signal generation unit and a second cancel signal generation unit. The first cancel signal generation unit generates, as a first cancel signal component, a cancel signal component corresponding to an image signal included in an analog signal output from a mixer. The second cancel signal generation unit generates, as a second cancel signal component, a cancel signal component corresponding to a leakage signal generated between an input and output of the mixer. The digital signal process unit includes subtractors for subtracting the first cancel signal component and the second cancel signal component from a signal component corresponding to a frequency band divided from an input signal to obtain a digital signal.

Abstract: A negative capacitance circuit is connected between a drain and a source of the mixer transistor. With this configuration, the negative capacitance circuit is connected in parallel to a parasitic capacitance generated between the drain and the source of the mixer transistor, and the parasitic capacitance can be canceled out in a wide band by the negative capacitance circuit connected in parallel.

Abstract: A source injection mixer includes an FET, an IF matching circuit between an IF port and a gate of the FET, and that matches impedance of the IF port and impedance of the gate as viewed from the IF port, a shorting stub of which one end is connected to a source of the FET and another end is grounded, and shorter than ¼ of an electric length at a frequency of LO signals, an LO matching circuit between an LO port and the source of the FET, and that matches impedance of the LO port and impedance of the source as viewed from the LO port, and an RF matching circuit between an RF port and a drain of the FET, and that matches impedance of the RF port and impedance of the drain as viewed from the RF port.

Abstract: A high frequency connection structure includes: a waveguide; a ridge coupler constituted by a conductor formed inside one end of the waveguide; a transmission line adjacent to the one end of the waveguide; an inductance adjustment structure which is provided between the ridge coupler and the transmission line and which adjusts ground inductance that is created due to a connection between the ridge coupler and the waveguide; and a wire which connects one end of the ridge coupler on a side of the transmission line and one end of the transmission line with each other.

Abstract: A resistive mixer includes a LO matching circuit inserted between the gate of an FET and a LO terminal, a bias circuit that is connected to the gate and applies a bias voltage to the gate, an RF matching circuit inserted between the drain of the FET and an RF terminal, and an IF matching circuit inserted between the drain and an IF terminal. The source of the FET is grounded. The impedance of the RF matching circuit seen from the drain of the FET at an IF frequency is open-circuit, and the impedance of the IF matching circuit seen from the drain of the FET at an RF frequency is open-circuit.

Abstract: A distributed mixer is configured of an artificial transmission line of which an input end is connected to an LO terminal and a terminal end is connected to an IF terminal, an artificial transmission line of which an input end is connected to an RF terminal, FETs that perform frequency synthesis of LO signals and RF signals and that are disposed following the artificial transmission lines and of which gates are connected to the artificial transmission line and sources are grounded, a bias circuit that applies gate bias voltage to a terminal end of the artificial transmission line, a terminating resistor that connects the terminal end of the artificial transmission line and a ground, and a plurality of transmission lines provided between the artificial transmission line and a drain of each FET.