Patents by Inventor Teruo Tanaka

Teruo Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120040908
    Abstract: Disclosed is a substance capable of promoting the repair of a fractured part in a fracture caused by an external force, fatigue or a disease. Also disclosed is a method for producing the substance. Further disclosed is a product capable of promoting the repair of a fracture, such as a food, a beverage and a feed, which comprises the fracture repair promoter. Specifically disclosed is a fracture repair promoter comprising, as an active ingredient, a fraction containing a milk-derived basic protein. In the promoter, the fraction containing the milk-derived basic protein is produced by contacting milk or a milk-derived raw material with a cation exchange resin to cause the adsorption of the basic protein on the cation exchange resin and eluting a fraction adsorbed on the resin by means of an eluent having a salt concentration of 0.1 to 1.0 M.
    Type: Application
    Filed: October 19, 2009
    Publication date: February 16, 2012
    Applicants: MEGMILK SNOW BRAND CO., LTD., KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORP.
    Inventors: Mizuho Kido, Toshiyuki Watanabe, Atsushi Danjo, Teruo Tanaka, Daisuke Uetsuji, Aiko Ono, Atsushi Serizawa
  • Patent number: 6899241
    Abstract: A waste collecting box to be placed on the roadside that includes a rear panel, side panels and a front panel wherein each of the side panels comprises two vertical segments, i.e., posterior and anterior segments jointed rotatably to a central junction such that the two segments can be folded at the junction with the junction moving inward until the two segments overlap with each other to form a flat structure; the rear vertical end of the posterior segment of each side panel is jointed rotatably to the lateral vertical end of the rear panel; and the front vertical end of the anterior segment of each side panel is jointed rotatably to the lateral vertical end of the front panel.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: May 31, 2005
    Assignee: Ai. Kankyo Co., Ltd.
    Inventor: Teruo Tanaka
  • Publication number: 20040004078
    Abstract: The waste collecting box of the present invention, once it is fixed on the roadside, can be folded into a flat layered structure. Therefore, if the box is folded when not in use, that is, while collection of wastes is not required, it will not markedly project towards the center of the road, and thus will not disturb the passage of passengers and motor vehicles. The folding and unfolding of the box after installment are quite easily performed through simple manual operations, and the box itself is sufficiently good in appearance as not to disgrace the scenery of the local area.
    Type: Application
    Filed: February 6, 2003
    Publication date: January 8, 2004
    Applicant: Ai. Kankyo Co., Ltd.
    Inventor: Teruo Tanaka
  • Patent number: 6514441
    Abstract: In order to manufacture a radial tire, first, in an average waveform recording step, a waveform component of radial force variation (RFV) by a molding factor in each molding machine, and a waveform component of RFV by a vulcanization factor in each vulcanizer are respectively acquired and recorded in a computer. In a waveform synthesizing step, a radial run-out (RRO, that is, vibrations resulting from non-uniformity of a tire surface) waveform of a green tire is substituted by an RFV waveform component and is made to overlap with respective RFV waveform components of waveforms of a molding factor and a vulcanization factor, thereby obtaining an RFV composite waveform. In a selection step, a circumferential position on the green tire at which an amplitude of the RFV composite waveform becomes minimum, and the circumferential position in a vulcanization mold are selected.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: February 4, 2003
    Assignee: Bridgestone Corporation
    Inventors: Teruo Tanaka, Yukio Saegusa
  • Patent number: 6510456
    Abstract: A computer connected to a plurality of computers, having: a storage area for storing data representative of properties of the plurality of computers relative to the computer; a data area for storing data to be used by the plurality of computers; and a program for determining a computer which holds data in the data area in accordance with a request for the data area. The computer can recover data lost from the computer from a proper area. Each of the properties of the plurality of computers is represented by a value determined by at least one of a computer fault occurrence frequency, a data transfer speed relative to the computer, an importance degree of data shared by processing programs of the plurality of computers. In accordance with the value in the storage area, the data in the data area,can be stored in multiples or in divisions.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: January 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Naoko Ikegaya, Taketoshi Sakuraba, Teruo Tanaka
  • Publication number: 20020029185
    Abstract: A brokerage server for performing brokerage service is provided to assist a user to select auction sites on the Internet when the user puts up own commodity at a plurality of auction sites simultaneously. The brokerage server, which resides between an information terminal of the user and the auction servers, in response to a process request from the information terminal, refers to an auction site information file to locate the auction sites suitable for the user's requirement and send information about the suitable auction sites to an information terminal so that the user can select the auction sites where the commodity is to be put up. After registration of the commodity at the selected auction servers, the brokerage server monitors trading status at the sites where the commodity is auctioned and performs the brokerage service until termination of the auction.
    Type: Application
    Filed: June 5, 2001
    Publication date: March 7, 2002
    Inventors: Teruo Tanaka, Masaaki Higuchi, Masaru Yamada
  • Patent number: 6321260
    Abstract: Before starting data transfer, the sender node sends the CONNECT message requesting security of hardware resources necessary for data transfer to the receiver node. Each node relaying the CONNECT message secures the CPU time and bandwidth necessary for data transfer and sends the CONNECT message to the receiver node. Upon receipt of the CONNECT message, the receiver node reserves the CPU time necessary for data reception and then sends the ACCEPT command to the sender node. The sender node receives the ACCEPT command and then sends a data packet.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: November 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Takeuchi, Takahiro Nakano, Masaaki Iwasaki, Teruo Tanaka
  • Patent number: 6306880
    Abstract: A triazole compound having the formula: wherein Ar1 represents a phenyl group which may be substituted; Ar2 represents a phenyl group which may be substituted; R0 represents a hydrogen atom or a lower alkyl; R1 represents a lower alkyl; R2 to R5 each represnet a hydrogen atom or an unsubstituted or halo substituted alkyl; n represnets 0 to 2; p represents 0 or 1; q, r and s each represent 0 to 2; A represents a 4- to 7-membered carbon ring or a 4- to 7-membered heterocyclic, not including 1,3-dioxan-5-yl. The compound of the present invention exhibits an excellent antifungal activity.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: October 23, 2001
    Assignee: Sankyo Company, Limited
    Inventors: Sadao Oida, Teruo Tanaka, Yawara Tajima, Toshiyuki Konosu, Atsushi Somada, Takeo Miyaoka, Hiroshi Yasuda
  • Publication number: 20010031778
    Abstract: A compound having the formula: 1
    Type: Application
    Filed: February 27, 2001
    Publication date: October 18, 2001
    Applicant: SANKYO COMPANY LIMITED
    Inventors: Sadao Oida, Teruo Tanaka, Yawara Tajima, Toshiyuki Konosu, Atsushi Somada, Takeo Miyaoka, Hiroshi Yasuda
  • Publication number: 20010031768
    Abstract: A compound having the formula: 1
    Type: Application
    Filed: February 27, 2001
    Publication date: October 18, 2001
    Applicant: SANKYO COMPANY LIMITED
    Inventors: Sadao Oida, Teruo Tanaka, Yawara Tajima, Toshiyuki Konosu, Atsushi Somada, Takeo Miyaoka, Hiroshi Yasuda
  • Patent number: 6300357
    Abstract: A triazole compound having the formula: wherein Ar1 represents a phenyl group which may be substituted, Ar2 represents a heterocyclic group which may be substituted, R0 represents a hydrogen atom or a lower alkyl; R1 represents a lower alkyl; R2 to R5 each represent a hydrogen atom or an unsubstituted or halo substituted alkyl; n represents 0 to 2; p represents 0 or 1; q, r and s each represent 0 to 2; A represents a 4- to 7-membered carbon ring or a 4- to 7-membered heterocyclic group. The compound of the present invention exhibits an excellent antifungal activity.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: October 9, 2001
    Assignee: Sankyo Company, Limited
    Inventors: Sadao Oida, Teruo Tanaka, Yawara Tajima, Toshiyuki Konosu, Atsushi Somada, Takeo Miyaoka, Hiroshi Yasuda
  • Patent number: 6298355
    Abstract: A storage control unit of a computer system in which main storage is shared between one through a plurality of processors, is provided with transfer control means for holding therein address information in a first area of the main storage, in which desired data specified by an arbitrary processor is stored, address information in a second area of the main storage device, to which the desired data is to be transferred, and information about the length of the desired data, and transfer means for reading the data stored in the first area and storing the data in the second area under the control of the transfer control means. Owing to these configurations, the storage control unit is capable of executing a copy of data from the first area to the second area separately from the processors according to instructions from each processor. Thus, the load on each processor can be reduced.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: October 2, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Teruo Tanaka, Tadayuki Sakakibara, Hiromitsu Maeda
  • Patent number: 5977152
    Abstract: A triazole compound having the formula: ##STR1## wherein Ar.sup.1 represents an optionally substituted phenyl, Ar.sup.2 represents an optionally substituted phenyl, R.sup.0 represents a hydrogen atom or a lower alkyl; R.sup.1 represents a lower alkyl; R.sup.2 to R.sup.5 represent a hydrogen atom or an unsubstituted or halo substituted alkyl, n represents 0 to 2; p represents 0 or 1; q, r and s each represent 0 to 2; and A represents a 1,3-dioxan-5-yl. The triazole compound of the present invention exhibits an excellent antifungal activity.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: November 2, 1999
    Assignee: Sankyo Company, Limited
    Inventors: Sadao Oida, Teruo Tanaka, Yawara Tajima, Toshiyuki Konosu, Atsushi Somada, Takeo Miyaoka, Hiroshi Yasuda
  • Patent number: 5892923
    Abstract: A parallel computer using a simply structured network which allows loads on message-transferring routes to be as equally distributed as possible and which eases possible conflict between different types of messages being transferred. Given a message to be transmitted, each processor (PE) on the network references a property setup table to determine property information depending on the message type and places the information into the message. For example, a route bit RB as the property information is set to "0" or "1" depending on whether the message is originated by the sending PE or is a message acknowledging the receipt of another message. According to the RB bit in the received message, a route instruction circuit in each exchange switch (EX) references a route instruction table to determine the message destination that depends on the receiving PE number designated by the message. Each EX has a plurality of virtual channel circuits.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: April 6, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiko Yasuda, Teruo Tanaka
  • Patent number: 5867679
    Abstract: A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.
    Type: Grant
    Filed: January 30, 1991
    Date of Patent: February 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Teruo Tanaka, Naoki Hamanaka, Koichiro Omoda, Shigeo Nagashima, Akira Muramatsu, Ikuo Yoshihara, Kazuo Nakao, Junji Nakagoshi, Kazuo Ojima
  • Patent number: 5857110
    Abstract: In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: January 5, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Tadayuki Sakakibara, Teruo Tanaka, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Hashimoto, Yasuhiro Inagami, Yoshiko Tamaki
  • Patent number: 5826049
    Abstract: In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: October 20, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Yasuhiro Ogata, Junji Nakagoshi, Naoki Hamanaka, Hiroyuki Chiba, Shinichi Shutoh, Tatsuo Higuchi, Shigeo Takeuchi, Taturu Toba, Teruo Tanaka
  • Patent number: 5822605
    Abstract: In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: October 13, 1998
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Tatsuo Higuchi, Tadaaki Isobe, Junji Nakagoshi, Shigeo Takeuchi, Tatsuru Toba, Yoshiko Yasuda, Teruo Tanaka, Takayuki Nakagawa, Yuji Saeki
  • Patent number: 5809539
    Abstract: In order to make use of row address lock mode of operation of a plurality of memory banks comprising synchronous DRAMs or the like and divided into a plurality of real bank groups, for example, for example, more than the memory banks are grouped into a plurality of logical groups each spanning the real bank groups. Addresses are allocated in unit of each logical group in a block-interleaving manner. When a series of requests issued by a given requester include a plurality of requests for accessing the same row address in the same memory bank, that requester requests that the row address be locked for access by the plurality of requests. The lock request is retained by a row address management unit. When a succeeding request from another requester requests access to a row address other than the locked address in the same memory bank, a priority circuit selects a predetermined number of requests from the initial requester having locked the memory in preference to a request made by the other requester.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: September 15, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Tadayuki Sakakibara, Teruo Tanaka, Yoshiko Tamaki
  • Patent number: 5754876
    Abstract: Preload register groups are respectively provided for the plurality of scalar processors which execute iterative processing in distributed manner. Each group consists of preload registers corresponding to a plurality of data arrays that appear in the iterative processing. According to address information about the plurality of arrays to be preloaded specified by any of the processors, a preload control unit reads partial data groups of one of the arrays to be first processed by all of the processors from the main storage in parallel. Then, the same operation is performed on another array. Subsequently, in the above-mentioned manner, remaining elements of the arrays are read from one array to another. A partial element group thus read sequentially is stored in the plurality of preload register groups in distributed manner.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: May 19, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiko Tamaki, Teruo Tanaka, Tadayuki Sakakibaraa