Abstract: In a parallel computer, there are provided a plurality of processor elements 1-1 to 1-n) connected to each other by a network (2); each of said processor elements including a local memory (6) for holding a program and data related thereto, a processor (3) for performing an instruction in said program, a circuit (5) for transferring the data to the other processor elements, and a circuit (4) for receiving the data sent from the other processor element; a memory area (92:8) constructed of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and a memory (92,8) constructed of a plurality of tag areas, provided for each of the reception data areas, for storing a valid data tag or an invalid data tag indicating that the data in the corresponding reception data area is valid or invalid; a transmitting circuit (5) for transmitting the data to be transmitted with attaching a data identifier predetermined by said data; a receiving circuit for writing the data into one of

Abstract: The high-temperature relaxation resistance of spring steel is improved by providing a specified composition of the steel, and subjecting that steel composition to a controlled heat treatment. The high-temperature relaxation resistance, which can not be estimated from the mechanical properties (e.g. strength and hardness) of steel materials at an ordinary temperature, is improved by these conditions which the inventors have found out from many experiments. Especially, the temper-softening resistance is enhanced by an increase of the Si content. The density of dislocation is lowered by providing fine carbides (MO.sub.2 C) serving as inhibitors for the migration of dislocation. These are precipitated by a controlled heat treatment without reducing hardness in the tempered state. Consequently, the obtained spring steel can be used operated in a high-temperature environment for a long time without a deterioration in its properties.

Abstract: In order to provide a pipe joint of stainless steel including more than 10% of Cr which joint has excellent shape memory effect, the stainless steel comprises up to 0.10% of C, 3.0 to 6.0% of Si, 6.0 to 25.0% of Mn, up to 7.0% of Ni, more than 10.0 to 17.0% of Cr, 0.02 to 0.30% of N, 2.0 to 10.0% of Co, and optionally one or more selected from 0.05 to 0.8% of Nb, 0.05 to 0.8% of V, 0.05 to 0.8% of Zr, 0.05 to 0.8% of Ti, up to 2.0% of Mo and up to 2.0% of Cu and the alloying components are balanced so that no .delta.-ferritic phase may substantially appear in the annealed condition. Since the joint is treated so that it has such a shape memory effect that it will recover the memorized original shape with a smaller diameter when heated to an appropriate temperature, it can fasten a pipe or pipes merely by heating.

Abstract: Compounds of formula (I): ##STR1## in which R.sup.a is a group of formula (II): ##STR2## where one of R' is a bond to the remainder of the compound, one more of R' is R.sup.2 and the others of R' are all hydrogen, R.sup.1 is hydrogen or methyl, R.sup.2 is hydrogen, optionally substituted alkyl, halogen, hydroxy, alkoxy, amino, alkanoylamino, alkanoyloxy, alkanoyl, carboxy, alkoxycarbonyl, cyano, --S(O).sub.j R.sup.9 where j is 0, 1 or 2 and R.sup.9 is alkyl, or --CONR.sup.6 R.sup.7 which is optionally substituted carbamoyl or heterocyclyl-carbonyl, --NR.sup.3 R.sup.4 is optionally substituted amino or heterocyclic, and --COOR.sup.5 is carboxy, --COO.sup.-, --COOM.sub.x, where M is a cation and x is the reciprocal of the valence of the cation M or protected carboxy and, where --COOR.sup.5 is carboxy, --COOM.sub.

Abstract: A shape memory stainless steel containing more than 10% by weight of Cr excellent in resistance to stress corrosion cracking and having sufficient function as a shape memory alloy, which comprises, by weight, up to 0.10% of C, 3.0 to 6.0% of Si, 6.0 to 25.0% of Mn, up to 7.0% of Ni, more than 10.0% and not more than 17.0% of Cr, 0.02 to 0.3% of N, 2.0 to 10.0% of Co and more than 0.2% and not more than 3.5% of Cu, and at least one selected from up to 2.0% of Mo, 0.05 to 0.8% of Nb, 0.05 to 0.8% of V, 0.05 to 0.8% of Zr, 0.05 or 0.8% of Ti, the balance being Fe and unavoidable impurities, the alloying components being adjusted so that a D value is not less than-26.0, wherein the D value is defined by the following equation:D=Ni+0.30.times.Mn+56.8.times.C+19.0.times.N+0.73.times.Co+Cu -1.85.times.[Cr+1.6.times.Si+Mo+1.5.times.(Nb+V+Zr+Ti)].

Abstract: A process for the production of a stainless steel strip having excellent spring characteristics as such and good formability, wherein a cold rolled strip of a stainless steel comprising, in addition to Fe, from 10.0 to 20.0% by weight of Cr, from 0.01 to 0.15% by weight of C, and at least one of Ni, Mn and Cu in an amount of from 0.1 to 4.0% by weight, is continuously passed through a continuous heat treatment furnace where it is heated to a temperature range for a two-phase of ferrite and austenite, rapidly cooled to provide a strip of a duplex structure, consisting essentially of ferrite and martensite, optionally temper rolled at a rolling reduction of not more than 10%, and continuously passed through a continuous heat treatment furnace to effect aging of not longer than 10 minutes.

Abstract: A computer system having a plurality of processors assigned first and second address portions are connected to a plurality of switch circuits. A first group transfer networks are connected to a corresponding first group of the plurality of switch circuits. Each of the transfer networks concurrently transfer data among the switch circuits. The switch circuits are provided to processors of a first kind arranged in a plurality of processor groups. The processor groups of the first kind include processors with different values for first address portions and the same value for second address portions. Additional transfer networks, processors and switches functioning in a similar manner are provided to expand the above system. In another embodiment of the present invention a data transfer network is provided having a plurality of processors for data transfer.

Abstract: Compounds of formula (I): ##STR1## in which R.sup.a is a group of formula (II): ##STR2## or a group of formula (III): ##STR3## (where one of R' is a bond to the remainder of the compound, one more of R' is R.sup.2 and the others of R' are all hydrogen), R.sup.1 is hydrogen or methyl, R.sup.2 is hydrogen, optionally substiuted alkyl, halogen, hydroxy, alkoxy, amino, alkanoylamino, alkanoyloxy, alkanoyl, carboxy, alkoxycarbonyl, cyano, --S(O).sub.j R.sup.9 (where j is 0, 1 or 2 and R.sup.9 is alkyl), or --CONR.sup.6 R.sup.7 (which is optionally substituted carbamoyl or heterocyclyl-carbonyl), R.sup.2a is hydrogen, alkyl or alkanoyl, --NR.sup.3 R.sup.4 is optionally substituted amino or heterocyclic, and --COOR.sup.5 is carboxy, --COO.sup.-, --COOM.sub.x (where M is a cation and x is the reciprocal of the valence of the cation M) or protected carboxy and, where --COOR.sup.5 is carboxy, --COOM.sub.

Abstract: Compounds of formula (I): ##STR1## wherein: one or both of R.sup.1 and R.sup.2 are selected from a variety of organic groups;R.sup.3 is an optionally substituted heterocycle; andR.sup.4 is hydrogen or optionally substituted alkyl or alkoxy.and salts and esters thereof have valuable antibiotic activity.

Abstract: A compiler for generating from a serially processed type source program described in a high level language the object codes to be executed in parallel by a parallel processor system which is composed of a plurality of processors marked with respective identification numbers and in which inter-processor data transfer system for identifying data for transfer by data identifiers is adopted. The serially executed source program is first translated to programs to be executed in parallel. The inter-processor data transfer processing is extracted from the flow of processings involved in executing the programs for parallel execution resulting from the above-mentioned translation, and all the interprocessor data transfer processings are attached with data identifiers such that no overlap takes place.

Abstract: In a multiprocessor digital computer system ID data, coupled with data for which inter-processor communication is desired, is communicated from one processor and held temporarily with data in a receiver buffer (associative memory) in a receiving processor. This ID is divided into main ID data MK and sub ID data SK. Main ID data MK is used for searching data from a receive buffer. The sub ID data SK are used as an ID of the data in the receive processor.

Abstract: A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data.

Abstract: A parallel processor system having a plurality of processor elements includes transfer information generation circuit for generating transfer information by adding to vector data a data identifier for the vector data and a destination processor element number, transmission circuit for sending the transfer information to a data communication path, receive circuit for holding the transfer information sent from the data communication path, and vector register for continuously reading related element data from the receive circuit based on the data identifiers generated by the transfer information generation circuit.

Abstract: A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected to the writing circuit and to the reading circuit, and which ensures the sequence of main storage references between said writing circuit and said reading circuit such that said reading circuit will not read the data elements that have not yet been written by said writing circuit among said group of data elements.

Abstract: In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.

Abstract: In a data transfer network of the present invention, each switch is designed such that when the partial address necessary for a given switch to determine another switch belonging to the succeeding stage, to which a packet is to be delivered from the given switch, is included in the first one of plural subpackets supplied to the given switch and each having the partial address, the given switch starts its switching operation upon arrival of the first subpacket. In a preferred embodiment, when the partial address necessary for the succeeding switch to make its switching operation is not included in the first subpacket, the partial addresses are exchanged between the subpackets by the preceding switch so that the said partial address is now included in the first subpacket.

Abstract: In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided.

Abstract: Process for producing steel strip of duplex structure wherein cold rolled strip of chromium stainless steel comprising, in addition to Fe, 10.0% to 20.0% of Cr, to 0.10% C, to 0.12% of N, the (C+N) being 0.01% to 0.20%, to 2.0% of Si, to 4.0% of Mn to 4.0% of Ni and to 4.0% of Cu, the {Ni+(Mn+Cu)/3} being not less than 0.5% but not more than 5.0%, is continuously passed through a heating zone where it is heated to form a two-phase of ferrite and austenite and the heated strip is cooled at a cooling rate sufficient to transform the austenite to martensite. The product has high strength and elongation reduced plane anisotropy and hardness of at least HV 200.

Abstract: Process for producing steel strip of duplex structure wherein cold rolled strip of chromiun stainless steel comprising, in addition to Fe, 10.0% to 20.0% of Cr, to 0.15% of C, to 0.12% of N, the (C+N) being 0.02% to 0.20%, to 2.0% of Si, to 1.0% of Mn and to 0.6% of Ni, is continuously passed through a heating zone where it is heated to form a two-phase of ferrite and austenite and the heated strip is cooled at a cooling rate sufficient to transform the austenite to martensite. The product has high strength and elongation reduced plane anisotropy and hardness of at least HV 200.

Abstract: In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.