Patents by Inventor Terutaka Mori

Terutaka Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110014727
    Abstract: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.
    Type: Application
    Filed: September 16, 2010
    Publication date: January 20, 2011
    Inventors: Akira YABUSHITA, Yasunori Narizuka, Susumu Kasukabe, Terutaka Mori, Etsuko Takane, Akio Hasebe, Kenji Kawakami
  • Publication number: 20090209053
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: March 20, 2009
    Publication date: August 20, 2009
    Inventors: Susumu KASUKABE, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 7541202
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: June 2, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 7390732
    Abstract: A semiconductor device capable of facilitating high density mounting at low cost without causing any defective conduction at the time of connection to a substrate, a mounting structure thereof and a method of fabrication thereof, characterized in that pyramidal bump electrodes are bonded onto pad electrodes arranged on a semiconductor chip to form the semiconductor device.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: June 24, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takayoshi Watanabe, Hidetaka Shigi, Susumu Kasukabe, Terutaka Mori
  • Patent number: 7351597
    Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: April 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
  • Publication number: 20080029763
    Abstract: A probe sheet or a connecting sheet with good transmission characteristics and flexibility comprising contact terminals capable of contacting at a plurality of points and in high density, without applying damages on an electrode pad which is a contact subject is provided. Further, a high-speed transmission circuit capable of designing signal wirings with aligned impedance to have wide width even with a thin insulating film is achieved to provide a probe sheet or a connecting sheet with reduced loss of high-speed transmission signals. Moreover, the transmission circuit is applied to a probe card using a probe sheet, an inspecting method of (a method of manufacturing) a semiconductor device using the same, and a connecting sheet having an excellent high-frequency characteristic.
    Type: Application
    Filed: April 26, 2007
    Publication date: February 7, 2008
    Inventors: Susumu Kasukabe, Terutaka Mori, Yasunori Narizuka, Norio Chujo
  • Publication number: 20080009082
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: September 12, 2007
    Publication date: January 10, 2008
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 7285430
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: October 23, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Publication number: 20070218572
    Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.
    Type: Application
    Filed: May 18, 2007
    Publication date: September 20, 2007
    Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
  • Patent number: 7219422
    Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: May 22, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
  • Patent number: 7198962
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: April 3, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Publication number: 20060094162
    Abstract: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.
    Type: Application
    Filed: October 20, 2005
    Publication date: May 4, 2006
    Inventors: Akira Yabushita, Yasunori Narizuka, Susumu Kasukabe, Terutaka Mori, Etsuko Takane, Akio Hasebe, Kenji Kawakami
  • Publication number: 20060043593
    Abstract: In the connecting apparatus for inspecting the semiconductor chip, in which contact terminals are electrically connected to each of the plurality of electrode pads formed on the semiconductor chips, a part of metal projections in the shape of quadrangular pyramid which constitute the contact terminals is composed of insulator in the present invention. Therefore, the inspection of semiconductor chips performed by simultaneously transmitting high-speed signals to the plurality of minute electrode pads arranged at a narrow pitch on the semiconductor chips can be realized.
    Type: Application
    Filed: July 20, 2005
    Publication date: March 2, 2006
    Inventors: Terutaka Mori, Yasunori Narizuka, Akira Yabushita, Etsuko Takane, Akio Hasebe, Kenji Kawakami
  • Publication number: 20040235207
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: June 23, 2004
    Publication date: November 25, 2004
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Publication number: 20040183556
    Abstract: Provided is a fabrication method of a semiconductor integrated circuit device which comprises forming a pushing mechanism by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal, placing an elastomer in the groove so that a predetermined amount exceeds the groove, and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. The present invention makes it possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.
    Type: Application
    Filed: January 29, 2004
    Publication date: September 23, 2004
    Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
  • Patent number: 6759258
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: July 6, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Publication number: 20030203521
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 30, 2003
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Patent number: 6566150
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: May 20, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Publication number: 20020182796
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Application
    Filed: June 17, 2002
    Publication date: December 5, 2002
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Patent number: 6455335
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: September 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe