Patents by Inventor Terutaka Mori

Terutaka Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020129323
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: October 9, 2001
    Publication date: September 12, 2002
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 6305230
    Abstract: A connection device and test system is capable of stable, low load damage-free probing of devices under test, which have many pins with a narrow pitch. Furthermore in order to achieve high speed exchange of electrical signals or so-called high frequency electrical signals, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: October 23, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 6197603
    Abstract: Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: March 6, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe