Patents by Inventor Teruyuki OHASHI

Teruyuki OHASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10394228
    Abstract: A combination of batch exchange carts that includes all of the feeders that supply components to be used in the post-changeover production from the multiple batch exchange units prepared in preparation space is decided based on the component information of feeders loaded on batch exchange carts used in the pre-changeover production and setup information of batch exchange carts that can be used for exchange memorized in memory device (component information of feeders loaded on batch exchange carts in preparation space), and then an operator is notified of the decided combination of batch exchange carts by sound or by the display of a mobile terminal or display device of production management computer.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 27, 2019
    Assignee: FUJI CORPORATION
    Inventor: Teruyuki Ohashi
  • Publication number: 20190230832
    Abstract: A production management device includes data management section having multiple correspondence data in which component types are linked to each product type of board product with reference codes, and process setting section for selecting, when circuit board is carried into component mounting machine in a family production, a product type for each of multiple unit boards based on identification information and sets the type of mounting process to be executed for each of multiple unit boards by selecting correspondence data for the selected product type.
    Type: Application
    Filed: October 20, 2016
    Publication date: July 25, 2019
    Applicant: FUJI CORPORATION
    Inventors: Teruyuki OHASHI, Tomokatsu KUBOTA
  • Patent number: 10236341
    Abstract: According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, first and second electrodes, and a first insulating film. The first semiconductor region includes first and second partial regions, and an intermediate partial region. The first electrode is separated from the first partial region. The second electrode includes first and second conductive regions. The second semiconductor region is provided between the first conductive region and the first electrode. The third semiconductor region is provided between the first conductive region and at least a portion of the second semiconductor region. The fourth semiconductor region includes third and fourth partial regions. The fourth partial region is positioned between the first conductive region and the first electrode. The first insulating film is provided, between the fourth partial region and the first electrode, and between the second semiconductor region and the first electrode.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Tatsuo Shimizu
  • Patent number: 10186572
    Abstract: A semiconductor device includes first, second, and gate electrodes. A first silicon carbide region of a first type is between the first and second electrodes and between the gate and second electrodes. Second and third silicon carbide regions of a second type are between the first electrode and first silicon carbide region. A portion of the first silicon carbide region is between the second and third silicon carbide regions. A fourth silicon carbide region of the first type is between the first electrode and second silicon carbide region. A fifth silicon carbide region of the first type is between the first electrode and third silicon carbide region. An insulation layer is between the gate electrode and second and third silicon carbide regions and sixth silicon carbide region of the second type. A second portion of the first silicon carbide region is between the second electrode and sixth silicon carbide region.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: January 22, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Kono, Teruyuki Ohashi
  • Patent number: 10165720
    Abstract: A production optimization device for a component mounting line executes, an intra present property optimization process of optimizing production of the component mounting line under conditions in which a selection range of members to use in the production is restricted to within a range of members actually owned by a user (present property), and a no-property-restriction optimization process of optimizing the production of the component mounting line under conditions in which restriction of the selection range of the members to use in the production is removed for at least a subset of the members are executed, and optimization results of the intra present property optimization process are displayed on a display device compared to optimization results of the no-property-restriction optimization process.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: December 25, 2018
    Assignee: FUJI CORPORATION
    Inventor: Teruyuki Ohashi
  • Publication number: 20180332748
    Abstract: There is provided a system 10 including at least one of inspection machines 20 and 22 and an NG board discharge machine 24 which moves an NG board to a checking position visible to a worker. The system 10 acquires positional information of a circuit board during conveyance, and stores the NG board by associating a work result for the NG board with the positional information. In this manner, the positional information of the NG board is acquired. Based on the positional information, it is determined whether or not the circuit board conveyed to the NG board discharge machine is the NG board. When the circuit board conveyed to the NG board discharge machine is the NG board, a checking-purpose working machine discharges the NG board to the checking position.
    Type: Application
    Filed: June 26, 2018
    Publication date: November 15, 2018
    Applicant: FUJI CORPORATION
    Inventors: Teruyuki Ohashi, Toshiya Suzuki
  • Publication number: 20180277634
    Abstract: A semiconductor device of an embodiment includes first and second electrodes, a first gate electrode, a semiconductor layer disposed between the first electrode and a band gap of the semiconductor layer being wider than a band gap of silicon, a silicon layer between the semiconductor layer and the first electrode, a metal layer between the semiconductor layer and the silicon layer, a first semiconductor region of a first-conductivity type in the semiconductor layer, a first silicon region of the first-conductivity type in the silicon layer, a second silicon region of a second-conductivity type in the first silicon region, a third silicon region of the second-conductivity type in the first silicon region and separated from the second silicon region, a first gate insulating layer, a fourth silicon region of the first-conductivity type in the second silicon region, and a fifth silicon region in the third silicon region.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke ASABA, Teruyuki OHASHI
  • Patent number: 10084046
    Abstract: A semiconductor device of an embodiment includes first and second electrodes, a first gate electrode, a semiconductor layer disposed between the first electrode and a band gap of the semiconductor layer being wider than a band gap of silicon, a silicon layer between the semiconductor layer and the first electrode, a metal layer between the semiconductor layer and the silicon layer, a first semiconductor region of a first-conductivity type in the semiconductor layer, a first silicon region of the first-conductivity type in the silicon layer, a second silicon region of a second-conductivity type in the first silicon region, a third silicon region of the second-conductivity type in the first silicon region and separated from the second silicon region, a first gate insulating layer, a fourth silicon region of the first-conductivity type in the second silicon region, and a fifth silicon region in the third silicon region.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Asaba, Teruyuki Ohashi
  • Patent number: 10074539
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: September 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Hiroshi Kono, Souzou Kanie, Tatsuo Shimizu
  • Patent number: 10051770
    Abstract: A system including at least one inspection machine and an NG board discharge machine which moves an NG board to a checking position visible to a worker. The system acquires positional information of a circuit board during conveyance, and stores the NG board by associating a work result for the NG board with the positional information. In this manner, the positional information of the NG board is acquired. Based on the positional information, it is determined whether or not the circuit board conveyed to the NG board discharge machine is the NG board. When the circuit board conveyed to the NG board discharge machine is the NG board, a checking-purpose working machine discharges the NG board to the checking position.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 14, 2018
    Assignee: FUJI MACHINE MFG. CO., LTD.
    Inventors: Teruyuki Ohashi, Toshiya Suzuki
  • Patent number: 10043883
    Abstract: A semiconductor device according to an embodiment includes a wide bandgap semiconductor layer, a gate electrode and a gate insulating film provided between the wide bandgap semiconductor layer and the gate electrode. The gate insulating film includes a first insulating film having a thickness of 7 nm or greater, a fixed charge film provided on the first insulating film, the fixed charge film containing fixed charge and a second insulating film provided on the fixed charge film, the second insulating film having a thickness of 7 nm or greater. The gate insulating film has a total thickness of 25 nm or greater.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 7, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Ryosuke Iijima, Tatsuo Shimizu
  • Publication number: 20180151365
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki OHASHI, Hiroshi KONO, Souzou KANIE, Tatsuo SHIMIZU
  • Patent number: 9950898
    Abstract: A semiconductor device according to an embodiment includes a plurality of circuit units each includes a first electrode, a second electrode, a switching element portion including first and second switching elements electrically connected between the first electrode and the second electrode, and a capacitor portion including a capacitor electrically connected between the first electrode and the second electrode and stacked with the switching element portion. In two of the adjacent circuit units, the switching element portion of one circuit unit and the capacitor portion of the other circuit unit are adjacent to each other, the capacitor portion of the one and the switching element portion of the other are adjacent to each other, the first electrode of the one and the first electrode of the other are adjacent to each other, and the second electrode of the one and the second electrode of the other are adjacent to each other.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: April 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuto Takao, Ryosuke Iijima, Tatsuo Shimizu, Teruyuki Ohashi
  • Publication number: 20180084684
    Abstract: The management computer sets a production job having the largest production volume to a production job having the Nth largest production volume of multiple production jobs to reference jobs of N groups respectively (S130), and determines arrangement positions of tape feeders on a pallet so that the production time required for processing the reference job is reduced based on the reference job (S140). In addition, the management computer performs grouping to allocate remaining production jobs excluding the reference job from the multiple production jobs to one of the N groups (S150) and determines arrangement positions of the tape feeders on the pallet based on the remaining production jobs (S160). Since a production job having a large production volume occupies a large proportion of the total production time required for processing the production jobs in the group, the total production time can be reduced by the production job.
    Type: Application
    Filed: March 5, 2015
    Publication date: March 22, 2018
    Applicant: FUJI MACHINE MFG. CO., LTD.
    Inventors: Teruyuki OHASHI, Yukihiro YAMASHITA
  • Publication number: 20180083095
    Abstract: A semiconductor device includes first, second, and gate electrodes. A first silicon carbide region of a first type is between the first and second electrodes and between the gate and second electrodes. Second and third silicon carbide regions of a second type are between the first electrode and first silicon carbide region. A portion of the first silicon carbide region is between the second and third silicon carbide regions. A fourth silicon carbide region of the first type is between the first electrode and second silicon carbide region. A fifth silicon carbide region of the first type is between the first electrode and third silicon carbide region. An insulation layer is between the gate electrode and second and third silicon carbide regions and sixth silicon carbide region of the second type. A second portion of the first silicon carbide region is between the second electrode and sixth silicon carbide region.
    Type: Application
    Filed: February 27, 2017
    Publication date: March 22, 2018
    Inventors: Hiroshi KONO, Teruyuki OHASHI
  • Patent number: 9916981
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Hiroshi Kono, Souzou Kanie, Tatsuo Shimizu
  • Publication number: 20180025910
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.
    Type: Application
    Filed: February 13, 2017
    Publication date: January 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki OHASHI, Hiroshi KONO, Souzou KANIE, Tatsuo SHIMIZU
  • Publication number: 20180012956
    Abstract: According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, first and second electrodes, and a first insulating film. The first semiconductor region includes first and second partial regions, and an intermediate partial region. The first electrode is separated from the first partial region. The second electrode includes first and second conductive regions. The second semiconductor region is provided between the first conductive region and the first electrode. The third semiconductor region is provided between the first conductive region and at least a portion of the second semiconductor region. The fourth semiconductor region includes third and fourth partial regions. The fourth partial region is positioned between the first conductive region and the first electrode. The first insulating film is provided, between the fourth partial region and the first electrode, and between the second semiconductor region and the first electrode.
    Type: Application
    Filed: February 22, 2017
    Publication date: January 11, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki OHASHI, Tatsuo Shimizu
  • Publication number: 20170365709
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.
    Type: Application
    Filed: February 13, 2017
    Publication date: December 21, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki OHASHI, Ryosuke IIJIMA, Hiroshi KONO, Tatsuo SHIMIZU
  • Publication number: 20170322548
    Abstract: A combination of batch exchange carts that includes all of the feeders that supply components to be used in the post-changeover production from the multiple batch exchange units prepared in preparation space is decided based on the component information of feeders loaded on batch exchange carts used in the pre-changeover production and setup information of batch exchange carts that can be used for exchange memorized in memory device (component information of feeders loaded on batch exchange carts in preparation space), and then an operator is notified of the decided combination of batch exchange carts by sound or by the display of a mobile terminal or display device of production management computer.
    Type: Application
    Filed: November 26, 2014
    Publication date: November 9, 2017
    Applicant: FUJI MACHINE MFG. CO., LTD.
    Inventor: Teruyuki OHASHI