Patents by Inventor Teruyuki UEDA
Teruyuki UEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11927860Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer iType: GrantFiled: April 11, 2022Date of Patent: March 12, 2024Assignee: SHARP DISPLAY TECHNOLOGY CORPORATIONInventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Teruyuki Ueda, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
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Patent number: 11804498Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.Type: GrantFiled: May 21, 2020Date of Patent: October 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tatsuya Kawasaki, Tohru Daitoh, Hajime Imai, Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Teruyuki Ueda
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Patent number: 11790867Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: December 7, 2022Date of Patent: October 17, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20230317739Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer.Type: ApplicationFiled: April 4, 2023Publication date: October 5, 2023Inventors: Hajime IMAI, Tohru DAITOH, Yoshihito HARA, Tetsuo KIKUCHI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Publication number: 20230307465Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.Type: ApplicationFiled: May 18, 2023Publication date: September 28, 2023Inventors: Hajime IMAI, Tohru DAITOH, Teruyuki UEDA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA, Tetsuo KIKUCHI
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Patent number: 11695020Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.Type: GrantFiled: December 11, 2020Date of Patent: July 4, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Hajime Imai, Tohru Daitoh, Teruyuki Ueda, Yoshihito Hara, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tetsuo Kikuchi
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Publication number: 20230100273Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Publication number: 20230082232Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.Type: ApplicationFiled: September 6, 2022Publication date: March 16, 2023Inventors: Tatsuya KAWASAKI, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Yoshiharu HIRATA, Yoshihito HARA
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Patent number: 11569324Abstract: An active matrix substrate includes a first TFT and a second TFT, in which the first TFT includes a first oxide semiconductor layer and a first gate electrode arranged on a part of the first oxide semiconductor layer with a first gate insulating layer interposed therebetween, the first gate insulating layer has a layered structure including a first insulating film and a second insulating film arranged on the first insulating film, the second TFT includes a second oxide semiconductor layer having a higher mobility than the first oxide semiconductor layer and a second gate electrode arranged on a part of the second oxide semiconductor layer with a second gate insulating layer interposed therebetween, and the second gate insulating layer includes the second insulating film and does not include the first insulating film, and the second TFT further includes a lower insulating layer including the first insulating film arranged between the second oxide semiconductor layer and a substrate.Type: GrantFiled: June 4, 2021Date of Patent: January 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Hajime Imai, Tohru Daitoh, Teruyuki Ueda, Yoshihito Hara, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
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Patent number: 11551629Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: April 20, 2022Date of Patent: January 10, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20220342246Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer iType: ApplicationFiled: April 11, 2022Publication date: October 27, 2022Inventors: Yoshihito HARA, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Publication number: 20220283674Abstract: An in-cell touch panel includes a plurality of source lines, a source redundant line, a touch sensor line formed in the same layer as the plurality of source lines or the source redundant line, an organic insulating layer formed in a layer above the touch sensor line, and a common electrode formed in a layer above the organic insulating layer. A contact hole in which part of the common electrode is arranged is formed in the organic insulating layer above the touch sensor line, and the common electrode is connected to the touch sensor line via the contact hole.Type: ApplicationFiled: March 1, 2022Publication date: September 8, 2022Inventors: MASAKI MAEDA, TOHRU DAITOH, HAJIME IMAI, YOSHIHITO HARA, TERUYUKI UEDA, YOSHIHARU HIRATA, TATSUYA KAWASAKI
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Publication number: 20220285405Abstract: An active matrix substrate includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate, in which each of oxide semiconductor TFT includes an oxide semiconductor layer including a first region and a second region having a specific resistance lower than a specific resistance of the first region, and a gate electrode disposed on at least a part of the first region with a gate insulating layer interposed therebetween, the gate insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer, and, when viewed from a normal direction of the substrate, the first insulating layer overlaps with the first region and does not overlap with the second region and the second insulating layer overlaps with the first region and at least a part of the second region.Type: ApplicationFiled: March 4, 2022Publication date: September 8, 2022Inventors: Hajime IMAI, Tohru DAITOH, Teruyuki UEDA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Publication number: 20220246105Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Patent number: 11322105Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: August 13, 2021Date of Patent: May 3, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Patent number: 11302718Abstract: Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interpType: GrantFiled: May 11, 2018Date of Patent: April 12, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Hideki Kitagawa, Teruyuki Ueda, Masahiko Suzuki, Setsuji Nishimiya, Toshikatsu Itoh
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Publication number: 20220077318Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.Type: ApplicationFiled: November 12, 2021Publication date: March 10, 2022Inventors: Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA, Tohru DAITOH, Hajime IMAI, Kengo HARA
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Patent number: 11215891Abstract: An active matrix substrate includes: a substrate; lower bus lines and upper bus lines; a lower insulating layer positioned between the lower bus lines and the upper bus lines; an oxide semiconductor TFT that are disposed in each pixel region and have an oxide semiconductor layer disposed on the lower insulating layer; pixel electrodes disposed in each pixel region; and wiring connection units arranged in a non-display region. Each wiring connection unit includes: a lower conductive layer formed using the same conductive film as the lower bus lines; an insulating layer that extends on the lower conductive layer and includes the lower insulating layer. The lower bus lines and the lower conductive layer have a first laminated structure including a metal layer and a transparent conductive layer that covers an upper surface and a side surface of the metal layer.Type: GrantFiled: May 21, 2020Date of Patent: January 4, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Tatsuya Kawasaki, Teruyuki Ueda, Hajime Imai, Tohru Daitoh
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Patent number: 11205729Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.Type: GrantFiled: March 6, 2019Date of Patent: December 21, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Teruyuki Ueda, Masamitsu Yamanaka, Tohru Daitoh, Hajime Imai, Kengo Hara
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Publication number: 20210390920Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: August 13, 2021Publication date: December 16, 2021Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH