Abstract: An active matrix substrate includes a source metal layer including a plurality of source bus lines and a gate metal layer including a plurality of gate bus lines, and a thin film transistor arranged in each pixel region, wherein: the thin film transistor includes a gate electrode, an oxide semiconductor layer arranged on the gate electrode with a gate insulating layer interposed therebetween, and a source electrode and a drain electrode, wherein the gate electrode is formed in the gate metal layer and is electrically connected to a corresponding one of the plurality of gate bus lines, the gate metal layer has a layered structure including a copper alloy layer and a copper layer arranged on the copper alloy layer, wherein the copper alloy layer is of a copper alloy including Cu and at least one additive metal element, wherein the additive metal element includes Al, and an Al content of the copper alloy is 2 at % or more and 8 at % or less.

Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.

Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.

Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.

Abstract: An active matrix substrate includes a first TFT (10), a second TFT (20) disposed per pixel, and a circuit including the first TFT. The first and second TFTs each include a gate electrode (102A, 102B), a gate insulating layer (103), an oxide semiconductor layer (104A, 104B), and source and drain electrodes in contact with an upper surface of the oxide semiconductor layer. The oxide semiconductor layer (104A, 104B) has a stacked structure including a first semiconductor layer (104e, 104c) in contact with the source and drain electrodes and a second semiconductor layer that is disposed on a substrate-side of the first semiconductor layer and that has a smaller energy gap than the first semiconductor layer. The oxide semiconductor layers (104A) and (104B) are different from each other in terms of the composition and/or the number of stacked layers. The first TFT has a larger threshold voltage than the second TFT.

Abstract: An array substrate including a spin-on glass layer formed of spin-on glass material, a first line disposed on a lower side with respect to the spin-on glass layer, the first line including a copper containing layer formed of copper or a copper alloy and a metal upper layer formed of one selected from a group consisting of titanium, an aluminum alloy, a copper alloy, a tungsten alloy, and a tantalum alloy, and the metal upper layer disposed on the copper containing layer and disposed between the copper containing layer and the spin-on glass layer, and a second line disposed on an upper side with respect to the spin-on glass layer and overlapping the first line in a plan view.

Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.

Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.

Abstract: In a semiconductor device, at least one thin-film transistor includes a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, and a drain electrode. The semiconductor layer has a multilayer structure that includes a plurality of channel formation layers including a first channel formation layer and a second channel formation layer, and at least one middle layer including a first middle layer provided between the first channel formation layer and the second channel formation layer. The first channel formation layer is disposed closer to the gate insulating layer than is the second channel formation layer, and is in contact with the gate insulating layer. The plurality of channel formation layers and the at least one middle layer are all an oxide semiconductor layer. The plurality of channel formation layers each have a mobility higher than that of the at least one middle layer.

Abstract: A semiconductor film 21 is provided so as to overlap with a light-shielding film 11 when viewed in a plan view. A second insulating film 30 has a contact hole CH1 that reaches a source electrode 22 and a drain electrode 23. A gate electrode 41 is provided on the second insulating film 30 so as to overlap with the semiconductor film 21 when viewed in a plan view, and at the same time, so as to overlap with none of the source electrode 22 and the drain electrode 23 when viewed in a plan view. A third insulating film 50 is provided on the second insulating film 30 so as to cover the gate electrode 41, and at the same time, so as to be in contact with the source electrode 22 and the drain electrode 23 through the contact hole CH1.

Abstract: An active matrix substrate includes a substrate, a TFT-containing layer which is supported on the substrate, and which includes a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes of the TFT, a metal wiring layer which is supported on the substrate and has a thickness of 400 nm or more, and an inorganic insulating layer which is thinner than the metal wiring layer, and is arranged on a substrate side of the metal wiring layer and is in contact with a lower surface of the metal wiring layer. The metal wiring layer has tensile stress and the inorganic insulating layer has compressive stress, and a ratio Sb/Sa of an absolute value Sb of a stress value of the inorganic insulating layer to an absolute value Sa of a stress value of the metal wiring layer is 0.6 or more and 1.7 or less.

Abstract: A spacer is fixed while an effect on a surface of an active matrix substrate is prevented. An active matrix substrate (1) includes a thin film transistor (11) which is provided on a substrate (2) and which has a recess made at a surface of the thin film transistor, and a spacer (13) fitted in the recess.

Abstract: An active matrix substrate includes a first TFT (10), a second TFT (20) disposed per pixel, and a circuit including the first TFT. The first and second TFTs each include a gate electrode (102A, 102B), a gate insulating layer (103), an oxide semiconductor layer (104A, 104B), and source and drain electrodes in contact with an upper surface of the oxide semiconductor layer. The oxide semiconductor layer (104A, 104B) has a stacked structure including a first semiconductor layer (104e, 104c) in contact with the source and drain electrodes and a second semiconductor layer that is disposed on a substrate-side of the first semiconductor layer and that has a smaller energy gap than the first semiconductor layer. The oxide semiconductor layers (104A) and (104B) are different from each other in terms of the composition and/or the number of stacked layers. The first TFT has a larger threshold voltage than the second TFT.

Abstract: A semiconductor film 21 is provided so as to overlap with a light-shielding film 11 when viewed in a plan view. A second insulating film 30 has a contact hole CH1 that reaches a source electrode 22 and a drain electrode 23. A gate electrode 41 is provided on the second insulating film 30 so as to overlap with the semiconductor film 21 when viewed in a plan view, and at the same time, so as to overlap with none of the source electrode 22 and the drain electrode 23 when viewed in a plan view. A third insulating film 50 is provided on the second insulating film 30 so as to cover the gate electrode 41, and at the same time, so as to be in contact with the source electrode 22 and the drain electrode 23 through the contact hole CH1.