Patents by Inventor Tetsuji Ueno
Tetsuji Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901220Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.Type: GrantFiled: July 23, 2020Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
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Patent number: 11848238Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.Type: GrantFiled: June 30, 2020Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tetsuji Ueno, Ting-Ting Chen
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Publication number: 20230268387Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Tetsuji UENO, Ting-Ting CHEN, Chen-Han WANG, Keng-Chu LIN
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Publication number: 20230242115Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Applicant: Taiwan Semiconductor For Manufactuing Co., Ltd.Inventors: Ting-Ting CHEN, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng
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Patent number: 11688766Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.Type: GrantFiled: April 4, 2022Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
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Patent number: 11626482Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.Type: GrantFiled: March 4, 2021Date of Patent: April 11, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Ting Chen, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng
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Publication number: 20220367278Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufafacturing Co, Ltd.Inventors: Chen-Han WANG, Keng-Chu LIN, Shuen-Shin LIANG, Tetsuji UENO, Ting-Ting CHEN
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Patent number: 11502166Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.Type: GrantFiled: November 20, 2020Date of Patent: November 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
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Patent number: 11456360Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.Type: GrantFiled: May 18, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
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Publication number: 20220285492Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Ting CHEN, Chen-Han WANG, Keng-Chu LIN, Shuen-Shin LIANG, Tsu-Hsiu PERNG, Tsai-Jung HO, Tsung-Han KO, Tetsuji UENO, Yahru CHENG
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Publication number: 20220223686Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.Type: ApplicationFiled: April 4, 2022Publication date: July 14, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
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Patent number: 11296187Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.Type: GrantFiled: July 23, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
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Publication number: 20210407856Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.Type: ApplicationFiled: June 30, 2020Publication date: December 30, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tetsuji Ueno, Ting-Ting Chen
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Publication number: 20210193506Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.Type: ApplicationFiled: July 23, 2020Publication date: June 24, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Chen-Han WANG, Keng-Chu LIN, Tetsuji UENO, Ting-Ting CHEN
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Publication number: 20210193799Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.Type: ApplicationFiled: November 20, 2020Publication date: June 24, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Chen-Han WANG, Keng-Chu LIN, Tetsuji UENO, Ting-Ting CHEN
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Publication number: 20200279920Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Tetsuji UENO, Ming-Hua YU, Chan-Lon YANG
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Patent number: 10658468Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.Type: GrantFiled: November 30, 2018Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
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Patent number: 10453925Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.Type: GrantFiled: April 1, 2016Date of Patent: October 22, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
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Publication number: 20190109194Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.Type: ApplicationFiled: November 30, 2018Publication date: April 11, 2019Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
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Publication number: 20170221709Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.Type: ApplicationFiled: April 1, 2016Publication date: August 3, 2017Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang