Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.

Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.

Abstract: There is provided a method of producing a semiconductor wafer, including: forming a compound semiconductor layer on a base wafer by epitaxial growth; cleansing a surface of the compound semiconductor layer by means of a cleansing agent containing a selenium compound; and forming an insulating layer on the surface of the compound semiconductor layer. Examples of the selenium compound include a selenium oxide. Examples of the selenium oxide include H2SeO3. The cleansing agent may further contain one or more substances selected from the group consisting of water, ammonium, and ethanol. When the surface of the compound semiconductor layer is made of InxGa1-xAs (0?x?1), the insulating layer is preferably made of Al2O3, and Al2O3 is preferably formed by ALD.

Abstract: A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.

Abstract: A method of producing a composite wafer including a semiconductor crystal layer, includes forming a sacrificial layer and the semiconductor crystal layer above a semiconductor crystal layer forming wafer in the stated order, etching the semiconductor crystal layer to partially expose the sacrificial layer and dividing the semiconductor crystal layer into a plurality of divided pieces, bonding the semiconductor crystal layer forming wafer and a transfer target wafer made of an inorganic material in such a manner that a first surface of the semiconductor crystal layer forming wafer faces and comes into contact with a second surface of the transfer target wafer, and etching the sacrificial layer to separate the transfer target wafer and the semiconductor crystal layer forming wafer from each other with the semiconductor crystal layer being left on the transfer target wafer.

Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer and a semiconductor crystal layer above a semiconductor crystal layer forming wafer, the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer being arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer, wherein the semiconductor wafer comprises a diffusion inhibiting layer that inhibits diffusion of a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer, at any cross-sectional position between (a) the interface of the semiconductor crystal layer forming wafer that faces the sacrificial layer and (b) a middle of the semiconductor crystal layer.

Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer, a first semiconductor crystal layer, and a second semiconductor crystal layer above a semiconductor crystal layer forming wafer, wherein the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer are arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer, a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer is contained in the first semiconductor crystal layer and the second semiconductor crystal layer as an impurity, and the concentration of the first atom in the second semiconductor crystal layer is lower than the concentration of the first atom in the first semiconductor crystal layer.

Abstract: Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Ea1 of the first crystal layer is larger than the electron affinity Ea2 of the second crystal layer.

Abstract: There is provided a method that includes forming a sacrificial layer and the semiconductor crystal layer on a semiconductor crystal layer formation wafer in the stated order, bonding together the semiconductor crystal layer formation wafer and a transfer-destination wafer such that a first surface of the semiconductor crystal layer and a second surface of the transfer-destination wafer face each other, and splitting the transfer-destination wafer from the semiconductor crystal layer formation wafer with the semiconductor crystal layer remaining on the transfer-destination wafer side, by etching away the sacrificial layer by immersing the semiconductor crystal layer formation wafer and the transfer-destination wafer wholly or partially in an etchant. Here, the transfer-destination wafer includes an inflexible wafer and an organic material layer, and a surface of the organic material layer is the second surface.

Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.

Abstract: There is provided a semiconductor device including: a first source and a first drain of a first-channel-type MISFET formed on a first semiconductor crystal layer, which are made of a compound having an atom constituting the first semiconductor crystal layer and a nickel atom, a compound having an atom constituting the first semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the first semiconductor crystal layer, a nickel atom, and a cobalt atom; and a second source and a second drain of a second-channel-type MISFET formed on a second semiconductor crystal layer, which are made of a compound having an atom constituting the second semiconductor crystal layer and a nickel atom, a compound having an atom constituting the second semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the second semiconductor crystal layer, a nickel atom, and a cobalt atom.

Abstract: There is provided a semiconductor device including a first channel-type first MISFET formed and a second channel-type second MISFET: a first source and a first drain of the first MISFET and a second source and a second drain of the second MISFET are made of the same conductive substance, and the work function ?M of the conductive substance satisfies at least one of relations respectively represented by (1) ?1<?M<?2+Eg2, and (2) |?M??1|?0.1 eV and |(?2+Eg2)??M|?0.1 eV, where ?1 represents an electron affinity of an N-type semiconductor crystal layer, and ?2 and Eg2 represent an electron affinity and a band gap of a crystal of a P-type semiconductor crystal layer.

Abstract: Provided is a semiconductor device including a first source and a first drain of a P-channel-type MISFET formed on a Ge wafer, which are made of a compound having a Ge atom and a nickel atom, a compound having a Ge atom and a cobalt atom, or a compound having a Ge atom, a nickel atom, and a cobalt atom, and a second source and a second drain of an N-channel-type MISFET formed on the Group III-V compound semiconductor, which are made of a compound having a Group III atom, a Group V atom, and a nickel atom, a compound having a Group III atom, a Group V atom, and a cobalt atom, or a compound having a Group III atom, a Group V atom, a nickel atom, and a cobalt atom.

Abstract: There is provided a method of producing a semiconductor wafer, including: forming a compound semiconductor layer on a base wafer by epitaxial growth; cleansing a surface of the compound semiconductor layer by means of a cleansing agent containing a selenium compound; and forming an insulating layer on the surface of the compound semiconductor layer. Examples of the selenium compound include a selenium oxide. Examples of the selenium oxide include H2SeO3. The cleansing agent may further contain one or more substances selected from the group consisting of water, ammonium, and ethanol. When the surface of the compound semiconductor layer is made of InxGa1-xAs (0?x?1), the insulating layer is preferably made of Al2O3, and Al2O3 is preferably formed by ALD.

Abstract: Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Ea1 of the first crystal layer is larger than the electron affinity Ea2 of the second crystal layer.

Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.

Abstract: A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.

Abstract: There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material.

Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.

Abstract: A dielectric layer may be formed by depositing the dielectric layer to an intermediate thickness and applying a nitridation process to the dielectric layer of intermediate thickness. The dielectric layer may then be deposited to the final, desired thickness.