Patents by Inventor Tetsuo Fujii

Tetsuo Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5403769
    Abstract: A process for producing a semiconductor device of the type having a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate; a first element formed in a region of the semiconductor layer and having a perimeter including a bottom; a second element formed in another region of the semiconductor layer; an insulating layer surrounding the perimeter of the first element, for electrically insulating and separating the first element from the second element and the semiconductor substrate; an electrical shield layer disposed between the insulating layer and the first element, surrounding the perimeter of the first element, and adapted to a reference electric potential applied thereto, for shielding the first element from an electrical fluctuation of the semiconductor substrate caused by the second element; and an electrode for applying the reference electric potential to the electrical shield layer.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: April 4, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventor: Tetsuo Fujii
  • Patent number: 5320705
    Abstract: A semiconductor pressure sensor of this invention is intended to provide a semiconductor pressure sensor having an excellent electrical isolation between the supporting means of the semiconductor pressure sensor and the semiconductor substrate, the semiconductor pressure sensor basically comprising a semiconductor substrate having a first semiconductor region in which; at least a semiconductor device is formed, a second semiconductor region and an isolated layer buried between the first and second semiconductor regions, a cavity provided in the second semiconductor region, the opening thereof existing on the mail surface of the second semiconductor region and a strain detecting portion consisting of the semiconductor device and provided in the first semiconductor region opposite to the cavity.
    Type: Grant
    Filed: August 18, 1993
    Date of Patent: June 14, 1994
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Yoshitaka Gotoh, Susumu Kuroyanagi, Osamu Ina
  • Patent number: 5313836
    Abstract: A semiconductor sensor for an accelerometer including a beam portion, consisting of a thin beam portion and a thick beam portion and supported by a solid member through the end of the thin beam portion, and a stopper portion provided at a position on an imaginary line along which a center of gravity of the thick beam portion moves. These components are integrally formed in a silicon substrate. Excessive displacement of the beam portion when excessive acceleration is applied is effectively suppressed by the stopper portion, and breakage of the thin beam portion due to excessive acceleration can be avoided.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: May 24, 1994
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Susumu Kuroyanagi, Yoshitaka Gotoh
  • Patent number: 5306942
    Abstract: A semiconductor layer is disposed on a semiconductor substrate and a first element is formed in a region of the semiconductor layer. A second element is formed in another region of the semiconductor layer. An insulating layer surrounds the perimeter of the first element, for electrically insulating and separating the first element from the second element and the semiconductor substrate. An electrical shield layer surrounds the perimeter of the first element, and is adapted to a reference electric potential applied thereto, for shielding the first element from an electrical fluctuation of the semiconductor substrate caused by the second element. An electrode is provided for applying the reference electric potential to the electrical shield layer.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: April 26, 1994
    Assignee: Nippondenso Co., Ltd.
    Inventor: Tetsuo Fujii
  • Patent number: 5138422
    Abstract: Disclosed is a semiconductor device which comprises a substrate, an insulating film formed at a predetermined region in the substrate or on the main surface of the substrate, a polycrystalline semiconductor layer formed on at least the insulating film, a single crystal semiconductor layer formed on at least the polycrystalline semiconductor layer, an isolation region formed to extend from the top main surface of the single crystal semiconductor layer to at least the surface of the insulating film, through the polycrystalline semiconductor layer, to electrically isolate a portion formed in the single crystal semiconductor layer surrounded by the isolation region from another portion formed in the single crystal semiconductor layer and not surrounded by the isolation region, at least a semiconductor device formed within the portion surrounded by the isolation region.
    Type: Grant
    Filed: November 6, 1991
    Date of Patent: August 11, 1992
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Susumu Kuroyanagi, Yukio Tsuzuki
  • Patent number: 5095349
    Abstract: A semiconductor pressure sensor of this invention is intended to provide a semiconductor pressure sensor having an excellent electrical isolation between the supporting means of the semiconductor pressure sensor and the semiconductor substrate, the semiconductor pressure sensor basically comprising a semiconductor substrate having a first semiconductor region in which at least a semiconductor device is formed, a second semiconductor region and an isolated layer buried between the first and second semiconductor regions, a cavity provided in the second semiconductor region, the opening thereof existing on the main surface of the second semiconductor region and a strain detecting portion consisting of the semiconductor device and provided in the first semiconductor region opposite to the cavity.
    Type: Grant
    Filed: June 7, 1989
    Date of Patent: March 10, 1992
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Yoshitaka Gotoh, Susumu Kuroyanagi, Osamu Ina
  • Patent number: 5063423
    Abstract: A tunnel insulating film of a three-layer structure, wherein an oxide film is interposed between nitrided oxide films, is formed on the surface of a semiconductor substrate. A first polysilicon film serving as a low-concentration impurity region is formed on the tunnel insulating film. An oxide film is formed on that region of the first polysilicon film, which corresponds to the tunnel insulating film, the oxide film having such a thickness that the film can serve as a stopper for impurity diffusion and can allow electrons to pass through. A second polysilicon film, having an impurity concentration higher than that of the first polysilicon film, is formed on the oxide film. The first and second polysilicon films constitute a floating gate. A third polysilicon film serving as a control gate is formed above the second polysilicon film, with an insulating layer interposed therebetween.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: November 5, 1991
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Minekazu Sakai, Akira Kuroyanagi
  • Patent number: 5028967
    Abstract: An achromatic lens for ultraviolet rays constituted by (A) high-purity silica glass having a purity of 99.9% or more, or fluorine-containing, high-purity silica glass having a purity of 99.9% or more; and (B) silica glass containing germanium dioxide or silica glass containing germanium dioxide and boron oxide.
    Type: Grant
    Filed: March 16, 1990
    Date of Patent: July 2, 1991
    Assignee: Tosoh Corporation
    Inventors: Nobusuke Yamada, Koji Tsukuma, Tetsuo Fujii, Hideaki Segawa, Shinichi Kondo, Keishi Honta
  • Patent number: 5019526
    Abstract: A method of manufacturing a semiconductor apparatus having a plurality of elements formed on a substrate comprises forming a pad oxidized film on the surface of the semiconductor substrate, forming a pattern of silicon nitride film to coat device areas on the pad oxidized film, and injecting boron ions into that surface of the pad oxidized film where no silicon nitride film is present, thereby to form a channel stopper region. Using the pattern of the silicon nitride film as a mask, a heat oxidized film is then formed on an elements separating region by heat oxidization, and ions of Si, N, C, or the like are injected into the surface of the heat oxidized film with such an acceleration energy that the ions are not injected into the silicon nitride film thereby to change the quality of the heat oxidized film.
    Type: Grant
    Filed: September 26, 1988
    Date of Patent: May 28, 1991
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hiroyuki Yamane, Yasushi Higuchi, Tetsuo Fujii
  • Patent number: 5017505
    Abstract: A first polysilicon film serving as an erase gate is deposited on the major surface of a semiconductor substrate on which a field oxide film is formed, so that the surface of the first polysilicon film is roughened. The surface of the first polysilicon film is thermally oxidized to form a first thermal oxide film thereon. During the oxidation, the roughened surface of the first polysilicon film is flattened, and is duplicated by the surface of the first thermal oxide film. A second polysilicon film is deposited on the roughened surface of the first thermal oxide film. The back surface of the second polysilicon film is roughened by the roughened surface of the first thermal oxide film. In this case, the surface of the second polysilicon film is also roughened. The roughened surface of the second polysilicon film is thermally oxidized in the same manner as described above to flatten its surface and to form a second thermal oxide film, the surface of which is roughened.
    Type: Grant
    Filed: February 23, 1989
    Date of Patent: May 21, 1991
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Toshio Sakakibara, Nobuyoshi Sakakibara
  • Patent number: 5017979
    Abstract: A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.
    Type: Grant
    Filed: April 28, 1989
    Date of Patent: May 21, 1991
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Minekazu Sakai, Akira Kuroyanagi
  • Patent number: 4975390
    Abstract: Herein disclosed is a semiconductor pressure sensor and a method of manufacture. The sensor includes a plate having a recess in its main surface. A diaphragm has a lower surface therof bonded to a first main surface of the plate and formed so as to have an upper surface having no holes therein. A piezoresistive layer is formed so as to be in contact with the diaphragm and is positioned so as to be at least partially over the recess. The resistance of the piezoresistive layer provides an indication of pressure applied to the diaphragm. The manufacturing method includes forming a piezoresistive layer of a single crystal substrate in a diaphragm without any recrystallization.
    Type: Grant
    Filed: December 8, 1987
    Date of Patent: December 4, 1990
    Assignee: Nippondenso Co. Ltd.
    Inventors: Tetsuo Fujii, Susumu Kuroyanagi, Akira Kuroyanagi, Tomohiro Funahashi, Minekazu Sakai, Shinji Yoshihara
  • Patent number: 4963505
    Abstract: Disclosed is a semiconductor device which comprises a substrate, an insulating film formed at a predetermined region in the substrate or on the main surface of the substrate, a polycrystalline semiconductor layer formed on at least the insulating film, a single crystal semiconductor layer formed on at least the polycrystalline semiconductor layer, an isolation region formed to extend from the top main surface of the single crystal semiconductor layer to at least the surface of the insulating film, through the polycrystalline semiconductor layer, to electrically isolate a portion formed in the single crystal semiconductor layer surrounded by the isolation region from another portion formed in the single crystal semiconductor layer and not surrounded by the isolation region, at least a semiconductor device formed within the portion surrounded by the isolation region.
    Type: Grant
    Filed: October 21, 1988
    Date of Patent: October 16, 1990
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Susumu Kuroyanagi, Yukio Tsuzuki
  • Patent number: 4924277
    Abstract: In a MIS transistor device, a gate electrode is formed on a first conductivity-type well region formed in a semiconductor substrate. By implanting impurities with the gate electrode and an element-isolating region made up of a field insulating film as a mask, an N-type diffusion layer having a higher impurity concentration than the first conductivity-type well region is formed on the sides of the gate electrode. A second conductivity-type diffusion layer of a first impurity concentration higher than the N-type diffusion layer is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on one side of the gate electrode. A second conductivity-type diffusion layer of a second high concentration is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on the other side of the gate electrode.
    Type: Grant
    Filed: April 20, 1989
    Date of Patent: May 8, 1990
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hiroyuki Yamane, Yasushi Higuchi, Tetsuo Fujii
  • Patent number: 4891984
    Abstract: First to third frames are formed by etching to penetrate a silicon substrate on the substrate. A plurality of thin cantilevered beams are formed in different lengths by cutting by etching the substrate in the frames; the beams formed in the first frame are formed perpendicular to the surface of the substrate to bend only in the X-axis direction, parallel to the surface of the substrate; the beams formed in the second frame are formed perpendicular to the surface of the substrate to bend only in the Y-axis direction, parallel to the surface of the substrate; and the beams formed in the third frame are formed to bend only in the Z-axis direction, perpendicular to the surface of the substrate. Masses are formed at the free ends of the beams, and piezo resistance layers are formed at the fixed ends.
    Type: Grant
    Filed: October 8, 1986
    Date of Patent: January 9, 1990
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Osamu Itoh
  • Patent number: 4870146
    Abstract: A process for producing a light color high softening point hydrocarbon resin, which comprises polymerizing an oil fraction obtained by condensing a fractionated component withdrawn in a gas phase from a recovery section of a fractionating tower located below the feeding section and above the bottom of the tower during the fractional distillation in the tower of a feed oil fraction having a boiling point within a range of from 140.degree. to 280.degree. C. selected among cracked oil fractions obtained by thermal cracking of petroleum.
    Type: Grant
    Filed: June 30, 1988
    Date of Patent: September 26, 1989
    Assignee: Tosoh Corporation
    Inventors: Yasushi Sakai, Tetsuo Fujii, Michio Saito, Motoaki Munekata, Akio Kiyohara
  • Patent number: 4867561
    Abstract: An apparatus for optically detecting the attachment state of extraneous matters to a translucent shield member. The optically detecting apparatus comprises a light-emitting unit having a plurality of light-emitting elements each emitting a light ray toward the translucent shield member, a photoelectric transducer unit having a plurality of transducer elements each receiving each of the light rays reflected on the translucent shield member, and a data processing unit coupled to the transducer unit. The transducer unit generates detection signals corresponding to the quantities of the received light rays and the data processing unit successively compares the level of each of the detection signals with a predetermined level to produce binary signals in accordance with the results of the comparison so that a binary signal pattern is defined at the respective transducer elements.
    Type: Grant
    Filed: August 18, 1987
    Date of Patent: September 19, 1989
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Hirohito Shioya, Tiaki Mizuno, Tadashi Kamada, Yasuaki Makino, Yoshimi Yoshino, Seiichiro Otake
  • Patent number: 4774556
    Abstract: A non-volatile semiconductor memory device comprises a semiconductor substrate of a first conduction type, an impurity buried layer of a second conduction type formed at the surface of the semiconductor substrate for constituting either one of a drain region or a source region, an epitaxial layer of a second conduction type formed at the surface of said impurity buried layer, an insulatiang partition wall extended vertically from the surface of the epitaxial layer surrounding operation regions in the impurity buried layer for defining the operation regions therein, at least one electron holding portion extended vertically with a predetermined distance from the operation regions and disposed within the insulating partition wall apart from the operation region, the impurity buried layer or the drain region by an insulation film of such a thickness as causing a tunnel effect, control gates disposed within the insulation partition wall disposed on every electron holding portions on the side opposite to the operat
    Type: Grant
    Filed: July 21, 1986
    Date of Patent: September 27, 1988
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Nobuyoshi Sakakibara, Toshio Sakakibara, Hiroshi Iwasaki
  • Patent number: 4393365
    Abstract: An automotive abnormality forecasting and warning method and system for issuing a voice and visual alarm when a signal representing the condition of an automotive inspection item exceeds a predetermined value, which comprise steps of calculating the cooling water temperature change rate in variable cycles, determining a calculation cycle corresponding to the detected water temperature and the calculated change rate from a memory storing the cooling water temperature, water-temperature-change rate and calculation cycle in a predetermined relation, judging whether the detected water temperature and the calculated change rate are in a predetermined water overheat region, and issuing a voice alarm on an overheating trend in response to more than a predetermined number of the judging operations.
    Type: Grant
    Filed: July 2, 1981
    Date of Patent: July 12, 1983
    Assignee: Nippondenso Co., Ltd.
    Inventors: Nobuo Kondo, Masanori Naganoma, Hitoshi Hibi, Tetsuo Fujii, Kunihiko Suzuki
  • Patent number: RE34893
    Abstract: A semiconductor pressure sensor of this invention is intended to provide a semiconductor pressure sensor having an excellent electrical isolation between the supporting means of the semiconductor pressure sensor and the semiconductor substrate, the semiconductor pressure sensor basically comprising a semiconductor substrate having a first semiconductor region in which at least a semiconductor device is formed, a second semiconductor region and an isolated layer buried between the first and second semiconductor regions, a cavity provided in the second semiconductor region, the opening thereof existing on the main surface of the second semiconductor region and a strain detecting portion consisting of the semiconductor device and provided in the first semiconductor region opposite to the cavity.
    Type: Grant
    Filed: March 22, 1993
    Date of Patent: April 4, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Yoshitaka Gotoh, Susumu Kuroyanagi, Osamu Ina