Patents by Inventor Tetsuo Fukushi
Tetsuo Fukushi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11710511Abstract: A semiconductor device includes a memory mat having: a plurality of memory cells; a sense amplifier connected to a memory cell selected from the plurality of memory cells; a first power supply wiring; a first switch connected between the sense amplifier and the first power supply wiring and made an ON state in operating the sense amplifier; and a second switch connected to the sense amplifier and made an ON state in operating the sense amplifier, a second power supply wiring arranged outside the memory mat and connected to the first power supply wiring, a third power supply wiring arranged outside the memory mat and connected to the sense amplifier via the second switch, and a short switch arranged outside the memory mat and connected between the second and third power supply wirings. Here, in operating the sense amplifier, the short switch is made an ON state.Type: GrantFiled: October 14, 2021Date of Patent: July 25, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuo Fukushi, Hiroyuki Takahashi, Muneaki Matsushige
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Publication number: 20220130434Abstract: A semiconductor device includes a memory mat having: a plurality of memory cells; a sense amplifier connected to a memory cell selected from the plurality of memory cells; a first power supply wiring; a first switch connected between the sense amplifier and the first power supply wiring and made an ON state in operating the sense amplifier; and a second switch connected to the sense amplifier and made an ON state in operating the sense amplifier, a second power supply wiring arranged outside the memory mat and connected to the first power supply wiring, a third power supply wiring arranged outside the memory mat and connected to the sense amplifier via the second switch, and a short switch arranged outside the memory mat and connected between the second and third power supply wirings. Here, in operating the sense amplifier, the short switch is made an ON state.Type: ApplicationFiled: October 14, 2021Publication date: April 28, 2022Inventors: Tetsuo FUKUSHI, Hiroyuki TAKAHASHI, Muneaki MATSUSHIGE
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Patent number: 10891986Abstract: The subject in the past is that there are a large number of data wirings in a semiconductor device including multiple memory cell arrays and that the area occupied by the data wirings is large. In a selected memory cell array among multiple memory cell arrays, a data wiring functions as a local wiring that transmits the data of the selected memory cell. In a memory cell array that is not selected among the memory cell arrays and is located between a data circuit and the selected memory cell array, the data wiring functions as a global wiring that transmits the data of a memory cell of the selected memory cell array.Type: GrantFiled: April 4, 2019Date of Patent: January 12, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuo Fukushi, Hiroyuki Takahashi
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Publication number: 20190333546Abstract: The subject in the past is that there are a large number of data wirings in a semiconductor device including multiple memory cell arrays and that the area occupied by the data wirings is large. In a selected memory cell array among multiple memory cell arrays, a data wiring functions as a local wiring that transmits the data of the selected memory cell. In a memory cell array that is not selected among the memory cell arrays and is located between a data circuit and the selected memory cell array, the data wiring functions as a global wiring that transmits the data of a memory cell of the selected memory cell array.Type: ApplicationFiled: April 4, 2019Publication date: October 31, 2019Inventors: Tetsuo Fukushi, Hiroyuki Takahashi
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Patent number: 9847108Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.Type: GrantFiled: November 13, 2012Date of Patent: December 19, 2017Assignee: Renesas Electronics CorporationInventors: Muneaki Matsushige, Atsunori Hirobe, Kazutaka Kikuchi, Tetsuo Fukushi
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Patent number: 9384788Abstract: A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit.Type: GrantFiled: January 13, 2016Date of Patent: July 5, 2016Assignee: Renesas Electronics CorporationInventors: Tetsuo Fukushi, Atsunori Hirobe, Muneaki Matsushige
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Publication number: 20160133301Abstract: A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit.Type: ApplicationFiled: January 13, 2016Publication date: May 12, 2016Inventors: Tetsuo Fukushi, Atsunori Hirobe, Muneaki Matsushige
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Publication number: 20160104516Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11_1 and a second memory area 11_2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm_ are disposed in a boundary area 18 between the first and second memory areas 11_1 and 11_2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.Type: ApplicationFiled: December 17, 2015Publication date: April 14, 2016Applicant: Renesas Electronics CorporationInventors: Tetsuo FUKUSHI, Atsunori HIROBE, Toshikatsu JINBO, Muneaki MATSUSHIGE
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Patent number: 9251868Abstract: An object of the invention is to make effective use of the structure of a multilayered semiconductor device that uses penetration electrodes in such a manner that the layered chips obtain stable internal power supply voltages with no increase in current consumption or in the area of the layered chips. Internal power supply generation circuits furnished in each of the layered core chips have their outputs commonly coupled via electrodes penetrating the layered core chips. This allows electrical charges to be shared among the core chips, optimizes internal power consumption of the multilayered semiconductor device as a whole, and inhibits fluctuations in the internal power supply voltages.Type: GrantFiled: April 1, 2015Date of Patent: February 2, 2016Assignee: Renesas Electronics CorporationInventors: Tetsuo Fukushi, Atsunori Hirobe, Muneaki Matsushige
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Patent number: 9251886Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm— are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.Type: GrantFiled: July 24, 2015Date of Patent: February 2, 2016Assignee: Renesas Electronics CorporationInventors: Tetsuo Fukushi, Atsunori Hirobe, Toshikatsu Jinbo, Muneaki Matsushige
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Publication number: 20150332752Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm— are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.Type: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuo FUKUSHI, Atsunori HIROBE, Toshikatsu JINBO, Muneaki MATSUSHIGE
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Publication number: 20150287441Abstract: An object of the invention is to make effective use of the structure of a multilayered semiconductor device that uses penetration electrodes in such a manner that the layered chips obtain stable internal power supply voltages with no increase in current consumption or in the area of the layered chips. Internal power supply generation circuits furnished in each of the layered core chips have their outputs commonly coupled via electrodes penetrating the layered core chips. This allows electrical charges to be shared among the core chips, optimizes internal power consumption of the multilayered semiconductor device as a whole, and inhibits fluctuations in the internal power supply voltages.Type: ApplicationFiled: April 1, 2015Publication date: October 8, 2015Inventors: Tetsuo FUKUSHI, Atsunori Hirobe, Muneaki Matsushige
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Patent number: 9123391Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . . , BLm_are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.Type: GrantFiled: November 18, 2013Date of Patent: September 1, 2015Assignee: Renesas Electronic CorporationInventors: Tetsuo Fukushi, Atsunori Hirobe, Toshikatsu Jinbo, Muneaki Matsushige
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Patent number: 8811103Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.Type: GrantFiled: January 3, 2014Date of Patent: August 19, 2014Assignee: Renesas Electronics CorporationInventors: Hiroyuki Takahashi, Tetsuo Fukushi
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Publication number: 20140146590Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . . , BLm_are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.Type: ApplicationFiled: November 18, 2013Publication date: May 29, 2014Applicant: Renesas Electronics CorporationInventors: Tetsuo FUKUSHI, Atsunori HIROBE, Toshikatsu JINBO, Muneaki MATSUSHIGE
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Publication number: 20140119145Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.Type: ApplicationFiled: January 3, 2014Publication date: May 1, 2014Applicant: Renesas Electronics CorporationInventors: Hiroyuki TAKAHASHI, Tetsuo Fukushi
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Patent number: 8681577Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.Type: GrantFiled: June 14, 2013Date of Patent: March 25, 2014Assignee: Renesas Electronics CorporationInventors: Hiroyuki Takahashi, Tetsuo Fukushi
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Publication number: 20130279281Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Inventors: Hiroyuki TAKAHASHI, Tetsuo FUKUSHI
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Patent number: 8482999Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.Type: GrantFiled: August 31, 2012Date of Patent: July 9, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Takahashi, Tetsuo Fukushi
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Publication number: 20120327732Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.Type: ApplicationFiled: August 31, 2012Publication date: December 27, 2012Inventors: Hiroyuki Takahashi, Tetsuo Fukushi