Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit configured to couple the memory cores with one of the bus-interface circuits in response to a predetermined logic level of the control signal.

Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.

Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A power supply circuit comprises: a first voltage booster circuit that receives a first clock signal having a fixed frequency, and supplies a voltage to a prescribed circuit; and a second voltage booster circuit that receives a second clock signal having a frequency corresponding to an operating frequency of the prescribed circuit, and supplies a voltage to the prescribed circuit.

Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.

Abstract: A semiconductor integrated circuit includes an output driver, a replica driver, a replica resistor, and an impedance adjustment circuit. The output driver is configured to be capable of changing current driving capability. The replica driver is configured to be capable of changing current driving capability. The replica resistor is connected to an output of the replica driver. The impedance adjustment circuit is configured to adjust the current driving capability of the output driver and the replica driver, based on an output voltage of the replica driver. In addition, the output driver, the replica driver, the replica resistor, and the impedance adjustment circuit are mounted in an integrated circuit package.

Abstract: A semiconductor integrated circuit includes an output driver, a replica driver, a replica resistor, and an impedance adjustment circuit. The output driver is configured to be capable of changing current driving capability. The replica driver is configured to be capable of changing current driving capability. The replica resistor is connected to an output of the replica driver. The impedance adjustment circuit is configured to adjust the current driving capability of the output driver and the replica driver, based on an output voltage of the replica driver. In addition, the output driver, the replica driver, the replica resistor, and the impedance adjustment circuit are mounted in an integrated circuit package.