Patents by Inventor Tetsuo Iijima
Tetsuo Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8466549Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. The third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: GrantFiled: September 23, 2011Date of Patent: June 18, 2013Assignee: Renesas Electronics CorporationInventors: Kentaro Ochi, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Publication number: 20120012978Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kentaro OCHI, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Patent number: 8035222Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: GrantFiled: December 15, 2010Date of Patent: October 11, 2011Assignee: Renesas Electronics CorporationInventors: Kentaro Ochi, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Publication number: 20110089558Abstract: There is provided a technology capable of reducing the mounting burden on the part of a customer which is a recipient of a package. Over a metal board, a single package and another single package are mounted together via an insulation adhesion sheet, thereby to form one composite package. As a result, as compared with the case where six single packages are mounted, the number of packages to be mounted is smaller in the case where three sets of the composite packages are mounted. This can reduce the mounting burden on the part of a customer.Type: ApplicationFiled: October 17, 2010Publication date: April 21, 2011Inventors: Akira MUTO, Akira Mishima, Takuro Kanazawa, Ochi Kentaro, Tetsuo Iijima, Katsuo Ishizaka
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Publication number: 20110084359Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: ApplicationFiled: December 15, 2010Publication date: April 14, 2011Inventors: Kentaro OCHI, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Patent number: 7872348Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: GrantFiled: June 9, 2010Date of Patent: January 18, 2011Assignee: Renesas Electronics CorporationInventors: Kentaro Ochi, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Publication number: 20100315786Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: ApplicationFiled: June 9, 2010Publication date: December 16, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kentaro OCHI, Akira MISHIMA, Takuro KANAZAWA, Tetsuo IIJIMA, Katsuo ISHIZAKA, Norio KIDO
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Patent number: 7482861Abstract: A power MOSFET Qp and a protection circuit 3 are formed over a semiconductor substrate to constitute a construction in which the power MOSFET Qp and the protection circuit 3 are electrically separated from each other. Then, a screening voltage is applied between the gate electrode and the source electrode of the power MOSFET Qp which is electrically separated from the protection circuit 3, thereby eliminating a power MOSFET Qp having a latent defect. Subsequently, a non-defective power MOSFET Qp and the protection circuit 3 are electrically connected by a bonding wire.Type: GrantFiled: August 28, 2000Date of Patent: January 27, 2009Assignee: Hitachi, Ltd.Inventors: Atsushi Fujiki, Tetsuo Iijima
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Publication number: 20080149972Abstract: ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.Type: ApplicationFiled: December 11, 2007Publication date: June 26, 2008Inventors: Katuo Ishizaka, Tetsuo Iijima
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Patent number: 7312501Abstract: ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.Type: GrantFiled: January 7, 2005Date of Patent: December 25, 2007Assignee: Renesas Technology Corp.Inventors: Katuo Ishizaka, Tetsuo Iijima
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Publication number: 20050151186Abstract: ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.Type: ApplicationFiled: January 7, 2005Publication date: July 14, 2005Inventors: Katsuo Ishizaka, Tetsuo Iijima
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Patent number: 6847058Abstract: ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.Type: GrantFiled: August 15, 2003Date of Patent: January 25, 2005Assignee: Renesas Technology Corp.Inventors: Katuo Ishizaka, Tetsuo Iijima
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Publication number: 20040155258Abstract: ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.Type: ApplicationFiled: August 15, 2003Publication date: August 12, 2004Applicant: Renesas Technology Corp.Inventors: Katsuo Ishizaka, Tetsuo Iijima
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Patent number: 6218889Abstract: A power MOSFET Qp and a protection circuit 3 are formed over a semiconductor substrate to constitute a construction in which the power MOSFET Qp and the protection circuit 3 are electrically separated from each other. Then, a screening voltage is applied between the gate electrode and the source electrode of the power MOSFET Qp which is electrically separated from the protection circuit 3, thereby eliminating a power MOSFET Qp having a latent defect. Subsequently, a non-defective power MOSFET Qp and the protection circuit 3 are electrically connected by a bonding wire.Type: GrantFiled: December 8, 1998Date of Patent: April 17, 2001Assignee: Hitachi, Ltd.Inventors: Atsushi Fujiki, Tetsuo Iijima
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Patent number: 6148536Abstract: A two-fluid nozzle for atomizing a liquid by mixing the liquid and a gas at high speed, wherein desired particle size is obtained at a low pressure, and a device employing the same nozzle for freezing and drying a liquid containing a biological substance are disclosed. The two-fluid nozzle which is provided with a first injection hole for injecting the liquid and a second injection hole for injecting the gas, wherein the second injection hole is provided around the outer periphery of the first injection hole; a revolving means (108 or 118) is provided to at least the front portion of the first injection hole for rending the liquid into revolving flow; and a revolving means (117) is provided to at least the front portion of the second injection holes for rending the gas into revolving flow, is suitable for atomization of a liquid containing a biological substance because the atomization at a low pressure is possible through operation of the revolving means for rending the gas and liquid into revolving flows.Type: GrantFiled: December 8, 1998Date of Patent: November 21, 2000Assignee: Nippon Telegraph and Telephone CorporationInventor: Tetsuo Iijima
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Patent number: 5656498Abstract: The present invention provides a method for manufacturing freeze-dried blood cells, stem cells and platelets comprising the steps of: pre-treating a liquid selected from the group consisting of blood including blood cells, bone marrow fluid (hemopoietic stem cells), and platelets in blood plasma, with a solution containing at least one substance selected from the group consisting of saccharide, biopolymer, acid and acid salt; conducting granulation of the aforementioned pre-treated liquid into a granules of a predetermined size; performing rapid cooling of the granules; and drying the resultant frozen material by sublimation of the water content contained therein.Type: GrantFiled: February 21, 1995Date of Patent: August 12, 1997Assignee: Nippon Telegraph and Telephone CorporationInventors: Tetsuo Iijima, Yoshikazu Ishii, Nobuhiro Funakoshi, Keiji Okada
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Patent number: 5642252Abstract: An improvement in conditions that protective functions of an insulated gate semiconductor device with a protection circuit incorporated therein are performed, an improvement in the cutoff of heating, the prevention of malfunctions and an improvement in ease of usage can be achieved.The insulated gate semiconductor device of the present invention comprises a power insulated gate semiconductor element (M9), at least one MOSFET (M1 through M7) for a protection circuit, for controlling the power insulated gate semiconductor element, a constant-voltage circuit using forward voltages developed across diodes (D2a through D2f) for the constant-voltage circuit, and voltage restricting diodes (D1 and D0a through D0d) for controlling the upper limit of a power supply voltage of the constant-voltage circuit. Power to be supplied to the voltage restricting diodes is supplied from an external gate terminal of the power insulated gate semiconductor element.Type: GrantFiled: August 15, 1994Date of Patent: June 24, 1997Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Kozo Sakamoto, Isao Yoshida, Shigeo Otaka, Tetsuo Iijima, Harutora Shono, Ken Uchid, Masayoshi Kobayashi, Hideki Tsunoda
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Power transistor device having collector voltage clamped to stable level over wide temperature range
Patent number: 5502338Abstract: A power transistor device is provided which has a function of clamping the collector voltage to a stable level for a wide range of temperature variations. In the power transistor device, a plurality of pn junctions are formed to fabricate Zener diodes in the polycrystalline silicon film in the form of rings. The ring configuration of the Zener diodes eliminates an end at the pn junction and prevents the junction surface from being exposed, making it possible to use as a stable Zener voltage the dielectric strength characteristic of the pn junction having a very small temperature coefficient.Type: GrantFiled: November 18, 1994Date of Patent: March 26, 1996Assignee: Hitachi, Ltd.Inventors: Minoru Suda, Masatoshi Nakasu, Tetsuo Iijima -
Patent number: 5397914Abstract: In a transistor where collector is connected to an inductive load and switching current flows, a Zener diode comprising structure of plural pn-junctions constituted in series form to a polysilicon is provided between collector and base. Further MOSFET is switch-controlled by control voltage formed based on Zener current flowing through the Zener diode, and current path in parallel form to the Zener diode is constituted. Since temperature characteristic coefficient of a Zener diode formed in a polysilicon film is very small, the reverse voltage generated in the inductive load can be set to stable voltage in spite of the temperature variation. Further the MOSFET is provided in parallel form, thereby relatively large ON-resistance value of the Zener diode can be decreased.Type: GrantFiled: April 27, 1993Date of Patent: March 14, 1995Assignee: Hitachi Ltd.Inventors: Minoru Suda, Masatoshi Nakasu, Tetsuo Iijima
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Patent number: 5196354Abstract: A semiconductor device has a semiconductor substrate, an insulated gate field-effect transistor section formed in the substrate and a peripheral section formed in the substrate and arranged to substantially surround the field-effect transistor section. A passivation layer of an organic material is provided over that part of the substrate in which the field-effect transistor section is not located. The device may be resin mold packaged for an enhanced humidity-resistance by making use of the fact tht the peripheral portion of the device is covered with organic resin.Type: GrantFiled: September 14, 1990Date of Patent: March 23, 1993Assignee: Hitachi, Ltd.Inventors: Shigeo Ohtaka, Akio Andoo, Tetsuo Iijima