Patents by Inventor Tetsuo Kikuchi

Tetsuo Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12635243
    Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs each including an oxide semiconductor layer, a lower gate electrode positioned on the substrate side of the oxide semiconductor layer, and an upper gate electrode positioned on the oxide semiconductor layer on a side opposite from the substrate, a plurality of source wiring lines extending in a column direction, a plurality of upper gate wiring lines extending in a row direction, and a plurality of lower gate wiring lines extending in the row direction. The plurality of lower gate wiring lines include a first gate wiring line, and the plurality of upper gate wiring lines include a second gate wiring line partially overlapping the first gate wiring line via the lower gate insulating layer and the upper gate insulating layer.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: May 19, 2026
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Masahiko Suzuki, Tetsuo Kikuchi, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata, Tohru Daitoh
  • Publication number: 20260093149
    Abstract: An active matrix substrate includes a plurality of TFTs, and a plurality of ESD protection elements disposed in a non-display region, each of the plurality of ESD protection elements being electrically connected to a corresponding wiring line. At least some TFTs of the plurality of TFTs include a first oxide semiconductor layer. Each of the ESD protection elements includes a second oxide semiconductor layer that is formed in a layer separated from the first oxide semiconductor layer and has a mobility lower than a mobility of the first oxide semiconductor layer.
    Type: Application
    Filed: September 26, 2025
    Publication date: April 2, 2026
    Inventors: Tetsuo KIKUCHI, Tohru Daitoh, Masahiko Suzuki, Setsuji Nishimiya, Hitoshi Takahata
  • Patent number: 12563838
    Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.
    Type: Grant
    Filed: May 14, 2024
    Date of Patent: February 24, 2026
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Tetsuo Kikuchi, Hideki Kitagawa, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata, Tohru Daitoh
  • Patent number: 12547280
    Abstract: An active matrix substrate is to be mounted on a display panel with a touch sensor function. The active matrix substrate includes a first layer provided with a touch sensor line, a second layer being above the touch sensor line and being provided with a pixel electrode, and a common electrode as a third layer formed between the first layer and the second layer. The common electrode functions as a touch sensor electrode by being connected to the touch sensor line and also functions as a counter electrode of the pixel electrode. The active matrix substrate further includes a first insulating layer formed between the first layer and the third layer, and a second insulating layer formed between the second layer and the third layer. The first insulating layer is formed of an organic resin film.
    Type: Grant
    Filed: February 22, 2024
    Date of Patent: February 10, 2026
    Assignee: Sharp Display Technology Corporation
    Inventors: Tetsuo Kikuchi, Tohru Daitoh, Setsuji Nishimiya, Hitoshi Takahata, Teruyuki Ueda
  • Patent number: 12513945
    Abstract: An active matrix substrate includes: a first oxide semiconductor layer including a first channel region; a first gate electrode disposed on the substrate side of the first oxide semiconductor layer; a channel protection layer disposed on a side of the first oxide semiconductor layer opposite to the substrate and covering the first channel region; a first TFT having a first source electrode and a first drain electrode in an upper layer of the channel protection layer; a second oxide semiconductor layer; a second gate electrode disposed on a side of the second oxide semiconductor layer opposite to the substrate; and the second TFT having a second source electrode and a second drain electrode disposed on an interlayer insulating layer that covers the second gate electrode, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed of the same layered oxide semiconductor film, the layered oxide semiconductor film has a layered structure including a high mobility oxide semicond
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: December 30, 2025
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Kengo Hara, Tohru Daitoh, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Hitoshi Takahata
  • Patent number: 12507482
    Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: December 23, 2025
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Hajime Imai, Tohru Daitoh, Yoshihito Hara, Tetsuo Kikuchi, Teruyuki Ueda, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
  • Publication number: 20250386693
    Abstract: An array substrate includes a first TFT including: a first insulating film disposed on an upper side of an insulating substrate; a first semiconductor film made of LTPS; a second insulating film; a first gate electrode composed of a first conducting film overlapping the first semiconductor film; a third insulating film; a first source relay electrode and a first drain relay electrode each composed of a second conducting film free of copper and connected to the first semiconductor film through first contact holes; a fourth insulating film; and a first source electrode and a first drain electrode each composed of a third conducting film containing copper and respectively connected to the first source relay electrode and the first drain relay electrode through second contact holes.
    Type: Application
    Filed: May 21, 2025
    Publication date: December 18, 2025
    Inventors: Tetsuo KIKUCHI, Hajime IMAI, Hitoshi TAKAHATA, Setsuji NISHIMIYA, Teruyuki UEDA, Yusuke INOUE
  • Publication number: 20250380510
    Abstract: An active matrix substrate includes a substrate, a plurality of gate signal lines, and a gate drive circuit. The gate drive circuit includes a shift register having a plurality of stages. The plurality of stages are constituted by a plurality of unit circuits each including a plurality of oxide semiconductor TFTs. The plurality of oxide semiconductor TFTs include at least one first TFT and at least one second TFT having lower mobility than does the first TFT. The at least one second TFT includes an oxide semiconductor TFT that becomes highest in drain-source electric field strength during operation of each unit circuit.
    Type: Application
    Filed: May 14, 2025
    Publication date: December 11, 2025
    Inventors: Masahiko Suzuki, Tetsuo Kikuchi, Setsuji Nishimiya, Hitoshi Takahata, Tohru Daitoh
  • Publication number: 20250366205
    Abstract: An active matrix substrate includes a scanning signal line drive circuit including an oxide semiconductor TFT. The oxide semiconductor TFT includes an oxide semiconductor layer including a channel region, a first contact region, and a second contact region, a gate electrode disposed on the channel region via a gate insulating layer, a source electrode, and a drain electrode. The oxide semiconductor layer has a layered structure including a first layer and a second layer that is located between the first layer and the gate insulating layer, is an uppermost layer of the oxide semiconductor layer, and has a lower mobility than the first layer. A thickness of the second layer in the channel region is equal to or more than 3.4% of a thickness of the gate insulating layer.
    Type: Application
    Filed: April 21, 2025
    Publication date: November 27, 2025
    Inventors: Tetsuo Kikuchi, Tohru Daitoh, Masahiko Suzuki, Setsuji Nishimiya, Hitoshi Takahata
  • Patent number: 12443080
    Abstract: An active matrix substrate includes a pixel TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode disposed so as to face the oxide semiconductor layer with the gate insulating layer interposed therebetween, a plurality of gate lines, an interlayer insulating layer provided so as to cover the gate electrode and the plurality of gate lines, a plurality of source lines provided on the interlayer insulating layer, an upper insulating layer provided so as to cover the plurality of source lines, and an organic insulating layer provided on the upper insulating layer. The interlayer insulating layer includes a first layer formed of silicon oxide, a second layer provided on the first layer and formed of silicon nitride, and a third layer provided on the second layer and formed of silicon oxide.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: October 14, 2025
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Hitoshi Takahata, Tohru Daitoh, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya
  • Publication number: 20250241067
    Abstract: A method for manufacturing an active matrix substrate includes (A) forming a plurality of TFTs on a substrate, (B) forming an interlayer insulating layer covering the plurality of TFTs, (C) forming a plurality of touch wiring lines on the interlayer insulating layer, (D) forming a first dielectric layer covering the plurality of touch wiring lines, (E) forming a common electrode on the first dielectric layer, (F) forming a second dielectric layer covering the common electrode, and (G) forming a plurality of pixel electrodes on the second dielectric layer. The interlayer insulating layer includes an organic insulating layer, and the forming an interlayer insulating layer (B) includes (B1) forming the organic insulating layer including a plurality of openings and a plurality of bump portions protruding upward by using a multi-tone photomask.
    Type: Application
    Filed: January 17, 2025
    Publication date: July 24, 2025
    Inventors: Hitoshi Takahata, Tohru Daitoh, Tetsuo Kikuchi, Setsuji Nishimiya, Masahiko Suzuki
  • Patent number: 12349414
    Abstract: Each first thin film transistor of a semiconductor device includes: a lower electrode; a first oxide semiconductor layer including a channel region and first and second contact regions; a gate electrode disposed on the channel region with a gate insulating layer interposed therebetween; and a source electrode and a drain electrode connected to the first contact region and the second contact region, respectively. When viewed from a normal direction of the substrate, at least a part of the channel region overlaps the lower electrode, and at least one of the first and second contact regions is located outside the lower electrode. The channel region has a layered structure including a lower layer, an upper layer located between the lower layer and the gate insulating layer, and a high mobility layer disposed between the lower layer and the upper layer and having mobility higher than mobility of the lower layer and the upper layer.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: July 1, 2025
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Tetsuo Kikuchi, Tohru Daitoh, Masahiko Suzuki, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata
  • Publication number: 20250121535
    Abstract: The purpose of the present invention is to provide a novel molded article having antibacterial or antiviral properties, a method for manufacturing the same, and the like. The present invention relates to a molded article 100 which contains a calcium compound 104 and a resin, and has a salt of inositol phosphate 102 with at least one metal element 103 selected from the group consisting of silver, zinc, and copper on a surface 101.
    Type: Application
    Filed: July 12, 2022
    Publication date: April 17, 2025
    Inventors: Mamoru AIZAWA, Kitaru SUZUKI, Ayano KATO, Tetsuo KIKUCHI
  • Patent number: 12162708
    Abstract: A sheet storage apparatus and a printing apparatus include simplified mechanisms for supporting a sheet and for guiding the sheet. A sheet storage device that can store a sheet discharged from a discharge port of a printing apparatus includes multiple flappers provided below the discharge port and arranged in a width direction of the sheet, each flapper being rotatable between a first posture in which the sheet discharged from the discharge port is guided downward in a gravitational direction by using a first surface, and a second posture in which the sheet is supported by using a second surface being different from the first surface; and a connecting unit which connects the plurality of flappers to one another.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: December 10, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Asai, Hiromasa Yoneyama, Tetsuo Kikuchi, Itaru Wada, Daiki Anayama
  • Patent number: 12142614
    Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: November 12, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hajime Imai, Tohru Daitoh, Teruyuki Ueda, Yoshihito Hara, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tetsuo Kikuchi
  • Publication number: 20240339460
    Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Inventors: Kengo HARA, Tohru DAITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA
  • Publication number: 20240329782
    Abstract: An active matrix substrate is to be mounted on a display panel with a touch sensor function. The active matrix substrate includes a first layer provided with a touch sensor line, a second layer being above the touch sensor line and being provided with a pixel electrode, and a common electrode as a third layer formed between the first layer and the second layer. The common electrode functions as a touch sensor electrode by being connected to the touch sensor line and also functions as a counter electrode of the pixel electrode. The active matrix substrate further includes a first insulating layer formed between the first layer and the third layer, and a second insulating layer formed between the second layer and the third layer. The first insulating layer is formed of an organic resin film.
    Type: Application
    Filed: February 22, 2024
    Publication date: October 3, 2024
    Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Setsuji NISHIMIYA, Hitoshi TAKAHATA, Teruyuki UEDA
  • Patent number: 12100711
    Abstract: An active matrix substrate includes a plurality of oxide semiconductor TFTs, and a plurality of wiring line connection sections, each of the plurality of wiring line connection sections includes a first connection electrode, an interlayer insulating layer extending over the first connection electrode, a wiring line contact hole formed in an insulating layer including the interlayer insulating layer, the wiring line contact hole exposing a part of a metal oxide layer of a first connection electrode, and a second connection electrode, and the second connection electrode is connected to a part of the metal oxide layer of the first connection electrode in the wiring line contact hole.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: September 24, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Tetsuo Kikuchi, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata, Tohru Daitoh
  • Publication number: 20240297181
    Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.
    Type: Application
    Filed: May 14, 2024
    Publication date: September 5, 2024
    Inventors: Masahiko SUZUKI, Tetsuo KIKUCHI, Hideki KITAGAWA, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA, Tohru DAITOH
  • Patent number: 12057454
    Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: August 6, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Hitoshi Takahata