Abstract: A method for manufacturing an active matrix substrate includes (A) forming a plurality of TFTs on a substrate, (B) forming an interlayer insulating layer covering the plurality of TFTs, (C) forming a plurality of touch wiring lines on the interlayer insulating layer, (D) forming a first dielectric layer covering the plurality of touch wiring lines, (E) forming a common electrode on the first dielectric layer, (F) forming a second dielectric layer covering the common electrode, and (G) forming a plurality of pixel electrodes on the second dielectric layer. The interlayer insulating layer includes an organic insulating layer, and the forming an interlayer insulating layer (B) includes (B1) forming the organic insulating layer including a plurality of openings and a plurality of bump portions protruding upward by using a multi-tone photomask.

Abstract: Each first thin film transistor of a semiconductor device includes: a lower electrode; a first oxide semiconductor layer including a channel region and first and second contact regions; a gate electrode disposed on the channel region with a gate insulating layer interposed therebetween; and a source electrode and a drain electrode connected to the first contact region and the second contact region, respectively. When viewed from a normal direction of the substrate, at least a part of the channel region overlaps the lower electrode, and at least one of the first and second contact regions is located outside the lower electrode. The channel region has a layered structure including a lower layer, an upper layer located between the lower layer and the gate insulating layer, and a high mobility layer disposed between the lower layer and the upper layer and having mobility higher than mobility of the lower layer and the upper layer.

Abstract: The purpose of the present invention is to provide a novel molded article having antibacterial or antiviral properties, a method for manufacturing the same, and the like. The present invention relates to a molded article 100 which contains a calcium compound 104 and a resin, and has a salt of inositol phosphate 102 with at least one metal element 103 selected from the group consisting of silver, zinc, and copper on a surface 101.

Abstract: A sheet storage apparatus and a printing apparatus include simplified mechanisms for supporting a sheet and for guiding the sheet. A sheet storage device that can store a sheet discharged from a discharge port of a printing apparatus includes multiple flappers provided below the discharge port and arranged in a width direction of the sheet, each flapper being rotatable between a first posture in which the sheet discharged from the discharge port is guided downward in a gravitational direction by using a first surface, and a second posture in which the sheet is supported by using a second surface being different from the first surface; and a connecting unit which connects the plurality of flappers to one another.

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

Abstract: An active matrix substrate is to be mounted on a display panel with a touch sensor function. The active matrix substrate includes a first layer provided with a touch sensor line, a second layer being above the touch sensor line and being provided with a pixel electrode, and a common electrode as a third layer formed between the first layer and the second layer. The common electrode functions as a touch sensor electrode by being connected to the touch sensor line and also functions as a counter electrode of the pixel electrode. The active matrix substrate further includes a first insulating layer formed between the first layer and the third layer, and a second insulating layer formed between the second layer and the third layer. The first insulating layer is formed of an organic resin film.

Abstract: An active matrix substrate includes a plurality of oxide semiconductor TFTs, and a plurality of wiring line connection sections, each of the plurality of wiring line connection sections includes a first connection electrode, an interlayer insulating layer extending over the first connection electrode, a wiring line contact hole formed in an insulating layer including the interlayer insulating layer, the wiring line contact hole exposing a part of a metal oxide layer of a first connection electrode, and a second connection electrode, and the second connection electrode is connected to a part of the metal oxide layer of the first connection electrode in the wiring line contact hole.

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

Abstract: A semiconductor device includes a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a first semiconductor layer made of an oxide semiconductor material of the first conductivity type, a first gate insulating layer provided on the first semiconductor layer, a first gate electrode located opposite to a channel region of the first semiconductor layer with the first gate insulating layer interposed therebetween, and a first source electrode. The second TFT includes a second semiconductor layer made of an oxide semiconductor material of the second conductivity type or a transparent semiconductor material of the second conductivity type, a second gate insulating layer provided on the second semiconductor layer, a second gate electrode located opposite to a channel region of the second semiconductor layer with the second gate insulating layer interposed therebetween, and a second source electrode.

Abstract: An active matrix substrate includes a pixel TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode disposed so as to face the oxide semiconductor layer with the gate insulating layer interposed therebetween, a plurality of gate lines, an interlayer insulating layer provided so as to cover the gate electrode and the plurality of gate lines, a plurality of source lines provided on the interlayer insulating layer, an upper insulating layer provided so as to cover the plurality of source lines, and an organic insulating layer provided on the upper insulating layer. The interlayer insulating layer includes a first layer formed of silicon oxide, a second layer provided on the first layer and formed of silicon nitride, and a third layer provided on the second layer and formed of silicon oxide.

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Abstract: An active matrix substrate includes a first TFT having an oxide semiconductor layer formed from a first oxide semiconductor film and a second TFT having an oxide semiconductor layer formed from a second oxide semiconductor film. The oxide semiconductor layer of each TFT includes a high-resistance region including a channel region and offset regions and low-resistance regions including a source contact region, a drain contact region, and interposed regions. The first TFT has a gate insulating layer including a first insulating film and a second insulating film. The second TFT has a gate insulating layer including the second insulating film but not including the first insulating film. A total length L1 of the offset regions of the first TFT in a channel length direction is greater than a total length L2 of the offset regions of the second TFT in the channel length direction.

Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer.

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

Abstract: A semiconductor device including a substrate, and a first circuit supported by the substrate and including a plurality of TFTs including a first TFT, wherein the first TFT includes a semiconductor layer, a lower gate electrode located on a side of the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via a lower gate insulating layer, and an upper gate electrode located on a side opposite to the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via an upper gate insulating layer, one of the lower gate electrode and the upper gate electrode is a first gate electrode and the other is a second gate electrode, a first signal is supplied to the first gate electrode, and a second signal different from the first signal is supplied to the second gate electrode, the first TFT has a threshold voltage between a high-level potential and a low-level potential of the first signal and between a high-level potential and a low-level potential of the sec

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.