Abstract: An active matrix substrate includes a substrate; a plurality of gate bus lines and a plurality of source bus lines; an oxide semiconductor TFT that includes an oxide semiconductor layer, a gate insulating layer, and a gate electrode; a pixel electrode; and an upper insulating layer. The oxide semiconductor layer includes a high resistance region, and a first region and a second region. The high resistance region includes a channel region, a first channel offset region, and a second channel offset region. The upper insulating layer is disposed so as to overlap the channel region, the first channel offset region, and the second channel offset region, and so as not to overlap any of the first region and the second region, when viewed from the normal direction of the main surface of the substrate.

Abstract: A focus adjustment device, comprising a processor that, during rapid shooting of still pictures, displays an image or performs processing for storage as still picture data based on a pixel signal output as a result of the first imaging operation from the image sensor, generates focus adjustment data by performing focus detection based on a pixel signal output as a result of the second imaging operation, and executes focus control, wherein the processor computes focus movement amount based on the focus adjustment data, and if the focus movement amount is larger than a predetermined value, and focus control based on the focus movement amount and the first imaging operation are executed in parallel, prohibits processing for storage as a still picture on image data based on a pixel signal of the first imaging operation.

Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs, a plurality of gate bus lines, a plurality of source bus lines, and at least one trunk wiring provided in a non-display region and transmitting a signal, and a plurality of other wirings, each of which is disposed so as to at least partially overlap the trunk wirings. The active matrix substrate includes a first metal layer, a second metal layer disposed above the first metal layer, and a third metal layer disposed above the second metal layer on the substrate. One of the first, second, and third metal layers includes a source bus line, and other layer includes a gate bus line. The trunk wiring is formed in two metal layer of the first, second and third metal layers.

Abstract: A focusing apparatus includes processing circuitry. The processing circuitry is configured to select an AF area indicating a defocus amount closest to a calculated moving object prediction equation among the latest defocus amounts detected for the plurality of AF areas, in a case where the moving object prediction equation is determined as being established, and the driving direction is determined as being the close-range direction. The moving object prediction equation is determined as being established when a divergence amount between the defocus amount equal to or larger than a predetermined number included in the history and the calculated moving object prediction equation is equal to or lower than a predetermined value.

Abstract: A sheet housing apparatus including a housing unit, which houses a sheet to be discharged from a discharging opening of a printer, and a pair of housing-side feet disposed on both sides, in a width direction, of the sheet housing apparatus. The sheet housing apparatus can be combined with the printer. The printer includes a pair of body-side feet disposed on both sides, in the width direction, of the printer.

Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode.

Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.

Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.

Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).

Abstract: An image sensor, comprising: a plurality of photo-diodes arranged divided in a specified pupil division direction, so that a pixel signal is generated by subjecting respective light flux, that passes through different exit pupil regions of an imaging optical systems for a single micro-lens, to photoelectric conversion, and a control circuit that implements an imaging mode for alternately and repeatedly executing a first imaging operation and a second imaging operation, wherein the first imaging operation combines pixel signals corresponding to the pupil division direction and generates and outputs a pixel signal for storage, and the second imaging operation generates and outputs a pixel signal corresponding to the pupil division direction, for focus detection.

Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

Abstract: A method for manufacturing an active matrix board includes (E) a step of forming a source contact hole and a drain contact hole in an interlayer insulating layer such that a portion of a source contact region of an oxide semiconductor layer and a portion of a drain contact region thereof are exposed and forming a connecting portion contact hole in the interlayer insulating layer and a lower insulating layer such that a portion of a lower conductive layer is exposed; and (F) a step of forming a source electrode, a drain electrode, and an upper conductive layer on the interlayer insulating layer; and the step (E) includes (e-1) a step of forming a photoresist film on the interlayer insulating layer and (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed.

Abstract: An imaging device, comprising an image sensor having image pixels and phase difference pixels, a phase difference detection section that detects a phase difference based on pixel data of the phase difference pixels, a pixel data calculation section that calculates pixel data of virtual imaging pixels at positions of the phase difference pixels, a degree of coincidence calculation section that calculates a degree of coincidence between each pixel data of the virtual imaging pixels that has been calculated, a reliability determination section that determines reliability of the phase difference detection result in accordance with the degree of coincidence, and a focus adjustment section that performs focus adjustment based on the phase difference detection result and the reliability.

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer positioned between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode that are electrically connected to the semiconductor layer, wherein the semiconductor layer has a stacked layer structure including a first oxide semiconductor layer including In, Ga, Zn, and Sn, and a second oxide semiconductor layer including In, Ga, Zn, and Sn, having a lower mobility than the first oxide semiconductor layer, and disposed on the first oxide semiconductor layer so as to be in direct contact with the first oxide semiconductor layer, the first and the second oxide semiconductor layers are amorphous, and a Sn atomic ratio R1 relative to all metal elements in the first oxide semiconductor layer and a Sn atomic ratio R2 relative to all metal elements in the second oxide semiconductor layer satisfy 0.8×R1?R2?1.2×R1.

Abstract: A sheet housing apparatus including a housing unit, which houses a sheet to be discharged from a discharging opening of a printer, and a pair of housing-side feet disposed on both sides, in a width direction, of the sheet housing apparatus. The sheet housing apparatus can be combined with the printer. The printer includes a pair of body-side feet disposed on both sides, in the width direction, of the printer. In a state in which the sheet housing apparatus is combined with the printer, the body-side feet and the housing-side feet are arranged not to overlap with each other in the width direction.

Abstract: An active matrix substrate includes a gate metal layer including a plurality of gate bus lines, and a thin film transistor arranged in each pixel region, wherein: the thin film transistor includes a gate electrode, an oxide semiconductor layer arranged on the gate electrode with a gate insulating layer interposed therebetween, wherein the gate electrode is formed in the gate metal layer and is electrically connected to a corresponding one of the plurality of gate bus lines, the gate metal layer has a layered structure including a copper alloy layer and a copper layer arranged on the copper alloy layer, wherein the copper alloy layer is of a copper alloy including Cu and at least one additive metal element, wherein the additive metal element includes Al, and an Al content of the copper alloy is 2 at % or more and 8 at % or less.

Abstract: An active matrix substrate 10 includes: switching elements 120 that are connected with gate lines and data lines provided on a substrate; pixel electrodes 130 that are connected with the switching elements 120; counter electrodes 140 that overlap with the pixel electrodes 130 when viewed in a plan view; a flattening film 154; and lines 142. The flattening film 154 covers the switching elements 120, and first contact holes CH1 that pass through the flattening film 154 are formed at positions that overlap with the lines 142 when viewed in a plan view. The pixel electrodes 130 and the counter electrodes 140 are arranged so that each of the same partially covers the flattening film 154. The line 142 and the counter electrode 140 are connected with each other in the first contact hole CH1.

Abstract: A focus adjustment device, comprising a processor having a focus region setting section, a focus detection section, a determination section and a control section, wherein the focus detection region setting section sets a first focus detection region, and a second focus detection region, that is contained in the first focus detection region and that is narrower than the first focus detection region, in an imaging region, the control section, when it is determined that that there is not a periodicity-containing subject for the first focus detection region, and it is determined that there is a periodicity-containing subject for the second focus detection region, performs a focus adjustment operation by selecting a phase difference that is closest to a phase difference that has been detected for the first focus detection region, among a plurality of phase differences that have been detected for the second focus detection region.

Abstract: A semiconductor device (100A) is provided with: a gate electrode (3); an oxide semiconductor layer (5); a thin-film transistor (101) including a gate insulating layer (4), a source electrode (7S), and a drain electrode (7D); an inter-layer insulating layer (11) arranged so as to cover the thin-film transistor (101) and come into contact with a channel area (5c) of the thin-film transistor (101); and a transparent electroconductive layer (19) arranged on the inter-layer insulating layer (11), the source electrode (7S) and the drain electrode (7D) each having a copper layer (7a), and the device being further provided with a copper oxide film (8) arranged between the source and drain electrodes and the inter-layer insulating layer (11). The inter-layer insulating layer (11) covers the drain electrode (7D) with the copper oxide film (8) interposed therebetween.