Patents by Inventor Tetsuo Nakano

Tetsuo Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040100562
    Abstract: Disclosed is a transmitting device which is capable of transmitting data even if a communication line is disconnected while the data is being transmitted, wherein the device is provided with a plurality of communication interfaces 109 to 112 connectable to a plurality of respective communication lines and transmits data through the communication interfaces. If a communication line is disconnected while data is being transmitted, the transmitting device selects an appropriate communication line based on predetermined criteria for communication line connection, drives a communication interface corresponding to the communication line to connect to the communication line, and transmits the data.
    Type: Application
    Filed: July 18, 2003
    Publication date: May 27, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Katsuei Ichikawa, Tetsuo Nakano, Shinya Imanishi
  • Patent number: 6671815
    Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: December 30, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Shigeya Tanaka, Hideo Maejima, Tetsuo Nakano
  • Patent number: 6645606
    Abstract: A substrate has a first surface and a second surface. A plurality of pads is formed on the first surfaces. Each pads has a Cu plating layer and an Au plating layer that is directly formed on the Cu plating layer. Al wiring or Au wiring is bonded with the pads. The thickness of the Au plating layer that is bonded with the Al wiring is less than 0.5 &mgr;m. Thickness of the Au plating layer that is bonded with the Au wiring is 0.05 &mgr;m or more.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: November 11, 2003
    Assignee: Denso Corporation
    Inventors: Tetsuo Nakano, Yukihiro Maeda, Yasutomi Asai, Takashi Nagasaka
  • Patent number: 6601752
    Abstract: At the step of printing a wiring portion of a ceramic substrate with a conductive adhesive for mounting an IC chip or a part such as a capacitor other than the IC chip, a wire bonding pad made of gold is formed by the ball bonding method or the like at the portion of the wiring portion to be wire-bonded. After the pad was formed and before the conductive adhesive is printed, a heat treatment is performed to cause a thermal diffusion between the wiring portion and the pad to improve the jointability therebetween.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: August 5, 2003
    Assignee: Denso Corporation
    Inventors: Yukihiro Maeda, Yuji Ootani, Tetsuo Nakano, Takashi Nagasaka
  • Publication number: 20030033197
    Abstract: A presentation method for advertisement information shown before and after the featured presentation in a movie theater, wherein the advertisement information is transmitted to the movie theater having a second terminal from a server via a telecommunication system. A server is accessed via an electric medium with a first terminal by an advertising client, and advertisement information is input onto the server by the advertising client. The server may be accessed from the second terminal by an exhibitor in order to show the advertisement information stored in the server. By receiving an access signal from the second terminal of the exhibitor, the selected advertisement information is transmitted from a range of advertisement information stored on the server, to the second terminal of the exhibitor.
    Type: Application
    Filed: August 9, 2001
    Publication date: February 13, 2003
    Inventors: Takashi Saga, Tetsuo Nakano
  • Publication number: 20020187319
    Abstract: A substrate has a first surface and a second surface. A plurality of pads is formed on the first surfaces. Each pads has a Cu plating layer and an Au plating layer that is directly formed on the Cu plating layer. Al wiring or Au wiring is bonded with the pads. The thickness of the Au plating layer that is bonded with the Al wiring is less than 0.5 &mgr;m. Thickness of the Au plating layer that is bonded with the Au wiring is 0.05 &mgr;m or more.
    Type: Application
    Filed: April 12, 2002
    Publication date: December 12, 2002
    Inventors: Tetsuo Nakano, Yukihiro Maeda, Yasutomi Asai, Takashi Nagasaka
  • Publication number: 20020099963
    Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.
    Type: Application
    Filed: February 7, 2002
    Publication date: July 25, 2002
    Inventors: Masahiro Iwamura, Shigeya Tanaka, Hideo Maejima, Tetsuo Nakano
  • Publication number: 20010020635
    Abstract: At the step of printing a wiring portion of a ceramic substrate with a conductive adhesive for mounting an IC chip or a part such as a capacitor other than the IC chip, a wire bonding pad made of gold is formed by the ball bonding method or the like at the portion of the wiring portion to be wire-bonded. After the pad was formed and before the conductive adhesive is printed, a heat treatment is performed to cause a thermal diffusion between the wiring portion and the pad to improve the jointability therebetween.
    Type: Application
    Filed: March 9, 2001
    Publication date: September 13, 2001
    Inventors: Yukihiro Maeda, Yuji Ootani, Tetsuo Nakano, Takashi Nagasaka
  • Patent number: 6258554
    Abstract: An industrially more advantageous method for the production of metabolites biologically synthesized via phosphoribosyl pyrophosphate (PRPP) is provided, making use of metabolically modified strains in which transketolase activity is deficient or reduced in comparison with the parent strain.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: July 10, 2001
    Assignee: Kyowa Hakko Kogyo Co., Ltd.
    Inventors: Masato Ikeda, Kazuyuki Okamoto, Tetsuo Nakano, Nozomu Kamada
  • Patent number: 6088808
    Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: July 11, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Shigeya Tanaka, Hideo Maejima, Tetsuo Nakano
  • Patent number: 5870594
    Abstract: The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.
    Type: Grant
    Filed: November 4, 1997
    Date of Patent: February 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Doi, Takehisa Hayashi, Tetsuo Nakano
  • Patent number: 5744331
    Abstract: Disclosed is a process for producing L-leucine which comprises culturing in a medium a microorganism belonging to the genus Escherichia and having resistance to a leucine analogue and an ability to produce L-leucine, allowing L-leucine to accumulate in the culture, recovering L-leucine therefrom.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: April 28, 1998
    Assignee: Kyowa Hakko Kogyo Co., Ltd.
    Inventors: Tetsuo Nakano, Masato Ikeda, Kuniki Kino, Satoru Furukawa
  • Patent number: 5737589
    Abstract: The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: April 7, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Doi, Takehisa Hayashi, Tetsuo Nakano
  • Patent number: 5734913
    Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: March 31, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Shigeya Tanaka, Hideo Maejima, Tetsuo Nakano
  • Patent number: 5629180
    Abstract: Disclosed is a process for producing an L-amino acid which comprises culturing a microorganism belonging to the genus Escherichia, having resistance to 2-ketobutyric acid and ability to produce the L-amino acid in a medium until the L-amino acid is accumulated in the medium, and recovering the L-amino acid therefrom.
    Type: Grant
    Filed: June 28, 1995
    Date of Patent: May 13, 1997
    Assignee: Kyowa Hakko Kogyo Co., Ltd.
    Inventors: Tetsuo Nakano, Motokazu Nakayama, Mariko Shitashige, Masato Ikeda, Satoru Furukawa
  • Patent number: 5480238
    Abstract: The invention aims at selecting a recording sheet discharge mode in accordance with user's priority of printing speed or printed image quality. In the thermal transfer printer, when discharge concurrent with printing is selected, a microcomputer operates to rotate a mode motor to close a transport passage between a guide member and a platen roller by means of a sheet discharge plate. Starting printing by rotating the platen roller in this state, the leading end of a recording sheet is delivered to a discharge opening, which is defined by the guide member and a guide plate, and introduced between sheet discharge rollers and idler rollers. When separate discharge after printing is selected, the microcomputer starts printing without rotating the mode motor. The sheet discharge plate closes the discharge opening defined by the guide member and the guide plate. The leading end of the recording sheet is delivered to the transport passage between the guide member and the platen roller.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: January 2, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Nakano, Yuichi Takano, Masami Takada
  • Patent number: 5460958
    Abstract: A process for the production of L-isoleucine using the microorganism, Escherichia coli H-8670 (FERM BP-4051) which has resistance to 0.2 g/l S-(2-aminoethyl)-L-cysteine or Escherichia coli H-8683 (FERM BP-4052) which has a resistance of 20 g/l of D-serine. The microorganism is cultured in a nutrient medium for a time and under conditions sufficient to produce L-isoleucine and the L-isoleucine is recovered from the medium.
    Type: Grant
    Filed: October 26, 1993
    Date of Patent: October 24, 1995
    Assignee: Kyowa Hakko Kogyo Co., Ltd.
    Inventors: Tetsuo Nakano, Tomoki Azuma, Yoshiyuki Kuratsu
  • Patent number: 5457790
    Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: October 10, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Shigeya Tanaka, Hideo Maejima, Tetsuo Nakano
  • Patent number: 5387809
    Abstract: A semiconductor integrated circuit device includes an interface corresponding to a relatively high signal level; an interface corresponding to a relatively low signal level; and an internal circuit made responsive to a signal through either interface for generating a signal to be transmitted to the other interface. The interface corresponding to a relatively high level, the internal circuit, and a drive control circuit constituting the input circuit and output circuit of the interface corresponding to a relatively low level are operated by an operating voltage corresponding to the relatively high level. An output element of the output circuit in the interface corresponding to a relatively low level, which is to be driven by the drive control circuit, is operated by an operating voltage corresponding to the relatively low level.
    Type: Grant
    Filed: January 13, 1992
    Date of Patent: February 7, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Mikio Yamagishi, Kazuo Koide, Tetsuo Nakano
  • Patent number: 5359727
    Abstract: In a clock generating apparatus or clock generator employing PLL (phase-locked loop) by controlling a VCO (voltage controlled oscillator) in response to an output obtained by phase-comparing a clock signal based on an output signal of the VCO with an externally applied timing signal, a range of an oscillating frequency of VCO is varied in accordance with a frequency variation in the timing signal. A clock generating apparatus is provided for each of plural information processing sections, so as to surely synchronize operations of data processings including data transfers between the respective sections. When a clock signal is distributed to each of the information processing sections, the clock signal outputted from the distributing circuit is phase-compared in order to control the VCO.
    Type: Grant
    Filed: March 2, 1990
    Date of Patent: October 25, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kozaburo Kurita, Tetsuo Nakano