Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitori

Abstract: A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.

Abstract: A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.

Abstract: A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.

Abstract: A seal ring (102) is formed in a manner to surround each ferroelectric capacitor (101). Additionally, a seal ring (103) is formed in a manner to surround a plurality of ferroelectric capacitors (101). Further, a seal ring (104) is formed in a manner to surround all of the ferroelectric capacitors (101) and along a dicing line (110) inside the dicing line (110).

Abstract: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.

Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitori

Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitori

Abstract: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.

Abstract: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.

Abstract: A conduction film 36 is formed in a larger design thickness value on a ferroelectric film 32 by MOCVD, and the entire surface of the conduction film 36 is anisotropically etched back, whereby the surface morphology of the conduction film 36 can be improved. The conduction film 36, whose surface morphology has been improved and which has been flattened, can be patterned by photolithography without the reflection of the incident exposure light in various directions, and a desired pattern as designed can be formed. The method for fabricating a semiconductor device can improve the surface morphology of a ferroelectric film formed by organic metal chemical vapor deposition.

Abstract: In the step of removing the photo-resist film formed on a substrate, dry ice particles, with a predetermined particle size, are blasted onto the photo-resist film at a predetermined pressure in a state of heating the substrate at room temperature or higher, such as 30 to 200° C., preferably at about 100° C.

Abstract: The semiconductor device fabrication method comprises the step of forming a first insulation film 48 on a semiconductor substrate 10 and a ferroelectric capacitor 42; the step of forming first interconnections 56a–56c; the step of forming a second insulation film 60; the step of planarizing the surface of the second insulation film 60; the step of making heat treatment with a heat treatment furnace to remove water from the second insulation film 60; the step of making heat treatment in a plasma atmosphere generated by using N2O gas or N2 gas; the step of removing water from the second insulation film 60 and nitriding the surface of the second insulation film 60; the step of forming a barrier film 62 on the second insulation film 60; the step of forming contact holes 68 in the barrier film 62 and the second insulation film 60; and the step of burying conductor plugs 70 in the contact holes 68.

Abstract: The semiconductor device fabrication method comprises the step of forming a first insulation film 48 on a semiconductor substrate 10 and a ferroelectric capacitor 42; the step of forming first interconnections 56a-56c; the step of forming a second insulation film 60; the step of planarizing the surface of the second insulation film 60; the step of making heat treatment with a heat treatment furnace to remove water from the second insulation film 60; the step of making heat treatment in a plasma atmosphere generated by using N2O gas or N2 gas; the step of removing water from the second insulation film 60 and nitriding the surface of the second insulation film 60; the step of forming a barrier film 62 on the second insulation film 60; the step of forming contact holes 68 in the barrier film 62 and the second insulation film 60; and the step of burying conductor plugs 70 in the contact holes 68.

Abstract: A seal ring (102) is formed in a manner to surround each ferroelectric capacitor (101). Additionally, a seal ring (103) is formed in a manner to surround a plurality of ferroelectric capacitors (101). Further, a seal ring (104) is formed in a manner to surround all of the ferroelectric capacitors (101) and along a dicing line (110) inside the dicing line (110).

Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitori

Abstract: A material of low viscosity is applied to a ferroelectric film 32 formed by MOCVD to form a buried layer 34. Then, anisotropic etching is made on the entire surface to remove the tops of convexities on the surface of the ferroelectric film 32, and the buried layer 34 remaining on the surface of the ferroelectric film 32 is removed. Thus, the surface morphology of the ferroelectric film 32 is improved and planarized. When the conduction film 36 and the ferroelectric film 32 are patterned by photolithography, prescribed patterns as designed can be formed without reflecting the incident exposure light in various directions. The method for fabricating a semiconductor device improves the surface morphology of the ferroelectric film formed by metal organic chemical vapor deposition.

Abstract: A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.

Abstract: A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.

Abstract: A material of low viscosity is applied to a ferroelectric film 32 formed by MOCVD to form a buried layer 34. Then, anisotropic etching is made on the entire surface to remove the tops of convexities on the surface of the ferroelectric film 32, and the buried layer 34 remaining on the surface of the ferroelectric film 32 is removed. Thus, the surface morphology of the ferroelectric film 32 is improved and planarized. When the conduction film 36 and the ferroelectric film 32 are patterned by photolithography, prescribed patterns as designed can be formed without reflecting the incident exposure light in various directions. The method for fabricating a semiconductor device improves the surface morphology of the ferroelectric film formed by metal organic chemical vapor deposition.