Patents by Inventor Tetsuo Yaegashi

Tetsuo Yaegashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060148108
    Abstract: A conduction film 36 is formed in a larger design thickness value on a ferroelectric film 32 by MOCVD, and the entire surface of the conduction film 36 is anisotropically etched back, whereby the surface morphology of the conduction film 36 can be improved. The conduction film 36, whose surface morphology has been improved and which has been flattened, can be patterned by photolithography without the reflection of the incident exposure light in various directions, and a desired pattern as designed can be formed. The method for fabricating a semiconductor device can improve the surface morphology of a ferroelectric film formed by organic metal chemical vapor deposition.
    Type: Application
    Filed: August 29, 2005
    Publication date: July 6, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Yuriko Kokubun, Tetsuo Yaegashi
  • Publication number: 20060115743
    Abstract: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.
    Type: Application
    Filed: February 28, 2005
    Publication date: June 1, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuo Yaegashi
  • Publication number: 20050205913
    Abstract: A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.
    Type: Application
    Filed: August 10, 2004
    Publication date: September 22, 2005
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuo Yaegashi