Patents by Inventor Tetsuro ISHIGURO
Tetsuro ISHIGURO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094459Abstract: An optical waveguide includes a diamond layer including a first surface, a second surface and a diamond layer including a complex defect; a first clad layer in contact with the first surface; a second clad layer in contact with the second surface and including a polarity; and a metal layer in Schottky contact with the second clad layer.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: FUJITSU LIMITEDInventors: Tetsuro ISHIGURO, Tetsuya MIYATAKE, Kenichi KAWAGUCHI, Toshiki IWAI, Yoshiyasu DOI, Shintaro SATO
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Publication number: 20230222375Abstract: A quantum circuit includes a plurality of first optical waveguides and a plurality of second optical waveguides formed on a substrate and each of which includes a single-photon source; a first multiplexer formed on the substrate and configured to condense first photons propagated through the plurality of first optical waveguides; a second multiplexer formed on the substrate and configured to condense second photons propagated through the plurality of second optical waveguides; a branching element configured to introduce the first photons condensed by the first multiplexer and the second photons condensed by the second multiplexer and branch the first photons and the second photons in a first direction and a second direction; a first detector configured to detect the first photons and the second photons branched in the first direction; and a second detector configured to detect the first photons and the second photons branched in the second direction.Type: ApplicationFiled: March 14, 2023Publication date: July 13, 2023Applicant: FUJITSU LIMITEDInventors: Tetsuro ISHIGURO, Kenichi KAWAGUCHI, Toshiyuki MIYAZAWA, Toshiki IWAI, Tetsuya MIYATAKE, Yoshiyasu DOI, Shintaro SATO
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Patent number: 10992269Abstract: A compound semiconductor device includes a first compound semiconductor layer containing a p-type impurity, a second compound semiconductor layer disposed over the first compound semiconductor layer and containing InGaN, an electron transit layer disposed over the second compound semiconductor layer, and an electron supply layer disposed over the electron transit layer.Type: GrantFiled: July 11, 2018Date of Patent: April 27, 2021Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, Junji Kotani, Norikazu Nakamura, Kozo Makiyama
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Patent number: 10847642Abstract: Disclosed is a compound semiconductor device that includes an electron transit layer; an electron supply layer disposed above the electron transit layer, and including a first region and a second region, the second region having a composition higher in Al than the first region and covering the first region from at least a bottom part of the second region; a first electrode disposed above the first region; and a second electrode disposed above the second region.Type: GrantFiled: June 21, 2018Date of Patent: November 24, 2020Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Junji Kotani, Norikazu Nakamura
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Patent number: 10600901Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer that is formed over the carrier transit layer and is made of InAlN; and a spacer layer that is formed between the carrier transit layer and the carrier supply layer and is made of at least one of AlGaN and InAlGaN.Type: GrantFiled: May 31, 2016Date of Patent: March 24, 2020Assignee: FUJITSU LIMITEDInventors: Junji Kotani, Norikazu Nakamura, Tetsuro Ishiguro
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Patent number: 10431656Abstract: A semiconductor crystal substrate includes a first buffer layer formed of a nitride semiconductor over a substrate, a second buffer layer formed of a nitride semiconductor on the first buffer layer, a first semiconductor layer formed of a nitride semiconductor on or over the second buffer layer, and a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer. The Fe concentration of the first buffer layer is higher than the C concentration of the first buffer layer. The C concentration of the second buffer layer is higher than the Fe concentration of the second buffer layer.Type: GrantFiled: August 28, 2017Date of Patent: October 1, 2019Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, Junji Kotani, Norikazu Nakamura
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Patent number: 10270404Abstract: A compound semiconductor device includes: a first layer of nitride semiconductor, the first layer being doped with Fe; a channel layer of nitride semiconductor above the first layer; and a barrier layer of nitride semiconductor above the channel layer, wherein the channel layer includes: a two-dimensional electron gas region in which the two-dimensional electron gas exists; and an Al-containing region between the two-dimensional electron gas region and the first layer, an Al concentration in the Al-containing region being 5×1017 atoms/cm3 or more and less than 1×1019 atoms/cm3.Type: GrantFiled: September 25, 2016Date of Patent: April 23, 2019Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Norikazu Nakamura, Atsushi Yamada
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Publication number: 20190020318Abstract: A compound semiconductor device includes a first compound semiconductor layer containing a p-type impurity, a second compound semiconductor layer disposed over the first compound semiconductor layer and containing InGaN, an electron transit layer disposed over the second compound semiconductor layer, and an electron supply layer disposed over the electron transit layer.Type: ApplicationFiled: July 11, 2018Publication date: January 17, 2019Applicant: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, Junji Kotani, Norikazu Nakamura, Kozo Makiyama
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Publication number: 20190006503Abstract: Disclosed is a compound semiconductor device that includes an electron transit layer; an electron supply layer disposed above the electron transit layer, and including a first region and a second region, the second region having a composition higher in Al than the first region and covering the first region from at least a bottom part of the second region; a first electrode disposed above the first region; and a second electrode disposed above the second region.Type: ApplicationFiled: June 21, 2018Publication date: January 3, 2019Applicant: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, JUNJI KOTANI, NORIKAZU NAKAMURA
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Patent number: 9997594Abstract: A compound semiconductor device includes: a GaN-based channel layer; a barrier layer of nitride semiconductor above the channel layer; and a cap layer of nitride semiconductor above the barrier layer, wherein the cap layer includes: a first region doped with Fe; and a second region above the first region, a concentration of Fe in the second region being lower than a concentration of Fe in the first region.Type: GrantFiled: September 22, 2016Date of Patent: June 12, 2018Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
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Publication number: 20180069086Abstract: A semiconductor crystal substrate includes a first buffer layer formed of a nitride semiconductor over a substrate, a second buffer layer formed of a nitride semiconductor on the first buffer layer, a first semiconductor layer formed of a nitride semiconductor on or over the second buffer layer, and a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer. The Fe concentration of the first buffer layer is higher than the C concentration of the first buffer layer. The C concentration of the second buffer layer is higher than the Fe concentration of the second buffer layer.Type: ApplicationFiled: August 28, 2017Publication date: March 8, 2018Applicant: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, JUNJI KOTANI, NORIKAZU NAKAMURA
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Patent number: 9899492Abstract: A compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; and a GaN cap layer formed over the electron supply layer, wherein the electron supply layer includes a first layer made of i-type AlxGa1-xN (0<x<1) and a second layer made of i-type AlyGa1-yN (x<y?1) and formed over the first layer.Type: GrantFiled: November 19, 2015Date of Patent: February 20, 2018Assignee: FUJITSU LIMITEDInventors: Atsushi Yamada, Tetsuro Ishiguro
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Publication number: 20170229566Abstract: A semiconductor device includes a substrate, a buffer layer including a nitride semiconductor and formed over the substrate, a composition gradient layer including a nitride semiconductor and formed over the buffer layer, a first semiconductor layer including a nitride semiconductor and formed over the composition gradient layer, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode that are formed over the second semiconductor layer. The buffer layer is formed of a material including GaN, the composition gradient layer is formed of a material including Al, and the proportion of Al in the composition gradient layer increases from a first side of the composition gradient layer closer to the buffer layer toward a second side of the composition gradient layer closer to the first semiconductor layer.Type: ApplicationFiled: December 20, 2016Publication date: August 10, 2017Applicant: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, NORIKAZU NAKAMURA
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Publication number: 20170125563Abstract: A compound semiconductor device includes: a first layer of nitride semiconductor, the first layer being doped with Fe; a channel layer of nitride semiconductor above the first layer; and a barrier layer of nitride semiconductor above the channel layer, wherein the channel layer includes: a two-dimensional electron gas region in which the two-dimensional electron gas exists; and an Al-containing region between the two-dimensional electron gas region and the first layer, an Al concentration in the Al-containing region being 5×1017 atoms/cm3 or more and less than 1×1019 atoms/cm3.Type: ApplicationFiled: September 25, 2016Publication date: May 4, 2017Applicant: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, NORIKAZU NAKAMURA, Atsushi Yamada
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Publication number: 20170125516Abstract: A compound semiconductor device includes: a GaN-based channel layer; a barrier layer of nitride semiconductor above the channel layer; and a cap layer of nitride semiconductor above the barrier layer, wherein the cap layer includes: a first region doped with Fe; and a second region above the first region, a concentration of Fe in the second region being lower than a concentration of Fe in the first region.Type: ApplicationFiled: September 22, 2016Publication date: May 4, 2017Applicant: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, NORIKAZU NAKAMURA
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Publication number: 20160359032Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer that is formed over the carrier transit layer and is made of InAlN; and a spacer layer that is formed between the carrier transit layer and the carrier supply layer and is made of at least one of AlGaN and InAlGaN.Type: ApplicationFiled: May 31, 2016Publication date: December 8, 2016Applicant: FUJITSU LIMITEDInventors: JUNJI KOTANI, NORIKAZU NAKAMURA, Tetsuro Ishiguro
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Patent number: 9502525Abstract: An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer.Type: GrantFiled: December 11, 2012Date of Patent: November 22, 2016Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura, Kenji Imanishi
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Publication number: 20160190278Abstract: A compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; and a GaN cap layer formed over the electron supply layer, wherein the electron supply layer includes a first layer made of i-type AlxGa1-xN (0<x<1) and a second layer made of i-type AlyGa1-yN (x<y?1) and formed over the first layer.Type: ApplicationFiled: November 19, 2015Publication date: June 30, 2016Applicant: FUJITSU LIMITEDInventors: Atsushi Yamada, Tetsuro Ishiguro
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Patent number: 9312341Abstract: A compound semiconductor device includes: a substrate; and a compound semiconductor lamination structure formed over the substrate, the compound semiconductor lamination structure including a buffer layer containing an impurity, and an active layer formed over the buffer layer.Type: GrantFiled: February 21, 2014Date of Patent: April 12, 2016Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Norikazu Nakamura
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Patent number: 9269799Abstract: A semiconductor apparatus includes: a substrate; a buffer layer formed on the substrate; a strained layer superlattice buffer layer formed on the buffer layer; an electron transit layer formed of a semiconductor material on the strained layer superlattice buffer layer; and an electron supply layer formed of a semiconductor material on the electron transit layer; the strained layer superlattice buffer layer being an alternate stack of first lattice layers including AlN and second lattice layers including GaN; the strained layer superlattice buffer layer being doped with one, or two or more impurities selected from Fe, Mg and C.Type: GrantFiled: July 29, 2013Date of Patent: February 23, 2016Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura