Patents by Inventor Tetsuro Sawai

Tetsuro Sawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060170071
    Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: abridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
    Type: Application
    Filed: January 20, 2006
    Publication date: August 3, 2006
    Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi, Makoto Tsubonoya, Kazunari Kurokawa
  • Publication number: 20060131724
    Abstract: A semiconductor apparatus comprises a substrate, a semiconductor chip fixedly secured on one side of the substrate, a spirally shaped coil formed on the other side of the substrate and electrically connected to the semiconductor chip, and a conductive pattern formed on a surface of the one side of the substrate facing to the semiconductor chip for stabilizing an inductance characteristic of the coil.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 22, 2006
    Applicants: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Akihiro Sato, Satoru Sekiguchi, Kiyokazu Kamado, Kazunari Kurokawa, Makoto Tsubonoya, Kiyoshi Mita, Yoichi Nabeta, Tetsuro Sawai, Toshikazu Imaoka
  • Publication number: 20050043004
    Abstract: A communication apparatus includes, as a plurality of communication functions, an amplifier for amplifying a received signal or a transmitting signal, a balun for converting an unbalanced signal to a balanced signal or converting a balanced signal to an unbalanced signal and a mixer for converting a frequency. A gain reducing unit for reducing a gain of a specific frequency band is installed in at least one of the plurality of communication functions. A band rejection filter, for example, serves as a gain reducing unit and is disposed between a pair of transistors. A plurality of band rejection filters may be so arranged as to be distributed to the plurality of communication functions.
    Type: Application
    Filed: August 11, 2004
    Publication date: February 24, 2005
    Inventors: Yasuhiro Kaizaki, Tetsuro Sawai
  • Patent number: 6538537
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: March 25, 2003
    Assignee: Sanyo Electric Co. Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Publication number: 20020113672
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Application
    Filed: April 25, 2002
    Publication date: August 22, 2002
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Patent number: 6400240
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: June 4, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Patent number: 6369655
    Abstract: A feedback circuit is connected between a drain electrode and a gate electrode of an FET. The feedback circuit is constituted by a series connection of a feedback amount adjusting resistor and an LC series resonance circuit. The LC series resonance circuit is constituted by a series connection of a capacitor and an inductor. The capacitance of the capacitor and the inductance of the inductor are set such that the LC series resonance circuit enters a short-circuited state with respect to an m-th harmonic by resonating at the frequency of the m-th harmonic, and the LC series resonance circuit enters an opened state with respect to a fundamental wave.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: April 9, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Publication number: 20010008383
    Abstract: A feedback circuit is connected between a drain electrode and a gate electrode of an FET. The feedback circuit is constituted by a series connection of a feedback amount adjusting resistor and an LC series resonance circuit. The LC series resonance circuit is constituted by a series connection of a capacitor and an inductor. The capacitance of the capacitor and the inductance of the inductor are set such that the LC series resonance circuit enters a short-circuited state with respect to an m-th harmonic by resonating at the frequency of the m-th harmonic, and the LC series resonance circuit enters an opened state with respect to a fundamental wave.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 19, 2001
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Publication number: 20010002116
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Application
    Filed: December 18, 2000
    Publication date: May 31, 2001
    Applicant: Sanyo Electric Co, Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Patent number: 6218890
    Abstract: A switching circuit device including a multi-gate field effect transistor having a plurality of gate electrodes between a drain electrode and a source electrode, a low resistor having its one end connected between the gate electrodes, and a high resistor connected between the other end of the low resistor and any one of the drain electrode, the source electrode and the end of the other low resistor.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: April 17, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tsutomu Yamaguchi, Seiichi Banba, Tetsuro Sawai, Hisanori Uda
  • Patent number: 6211754
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: April 3, 2001
    Assignee: Sanyo Electric Co., Ltd,
    Inventors: Masao Nishida, Tetsuro Sawai
  • Patent number: 5590412
    Abstract: A communication apparatus for use in a portable telephone is disclosed which has a transmit-receive common amplifier for amplifying a transmitted signal or received signal, and a mixer for frequency-mixing the transmitted signal or the received signal with a local oscillator output, wherein connection between the mixer and an input side of the amplifier and connection between the mixer and an output side of the amplifier are made by means of respective signal-path selector switches. During reception, a deep bias is applied to an FET of the transmit-receive common amplifier to reduce current consumption, and during transmission, a shallow bias is applied to the FET of the transmit-receive common amplifier for increased output.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: December 31, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Sawai, Hisanori Uda, Toshikazu Hirai, Toshikazu Imaoka, Yasoo Harada, Keiichi Honda, Masao Nishida
  • Patent number: 5585676
    Abstract: An IC chip characterized in that at least two input pads and at least two output pads are respectively disposed symmetrical to each other about the center of the IC chip, at least two input/output pads are disposed symmetrical to each other about the center, at least one supply voltage pad is disposed in each of four equal sections formed by longitudinally and laterally dividing the IC chip, and at least one control voltage pad is disposed in each of these four sections. The IC chip can be connected by bonding to various types of IC packages having different configurations of the pins only by mounting in a proper direction without causing the bonding wires to bridge over the other constituent elements or to cross each other.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: December 17, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Tetsuro Sawai, Toshikazu Imaoka, Toshikazu Hirai, Yasoo Harada
  • Patent number: 5559457
    Abstract: A double-balanced mixer circuit which consumes less power, and is capable of operating on a low voltage power source, because an output of a first signal having a phase lag of 90.degree. from a first frequency signal and an output of a second signal having a phase lead of 90.degree. over the first frequency signal are provided by means of a first phase shifter, an output of a third signal having a phase lag of 90.degree. from a second frequency signal and an output of fourth signal having a phase lead of 90.degree. over the second frequency signal are provided by means of a second phase shifter, thereby generating a radio frequency signal by mixing the first signal and the third signal in a first dual gate circuit, and generating a radio frequency signal by mixing the second signal and the fourth signal in a second dual gate circuit.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: September 24, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Tetsuro Sawai, Toshikazu Imaoka, Toshikazu Hirai, Yasoo Harada
  • Patent number: 5528509
    Abstract: The S-parameters of a transistor are measured at a plurality of bias points, and using a tentatively decided load resistance value, the S-parameters on the load curve are examined, based on which the power gain and input/output power characteristics are obtained to determine the optimum load. Then, by using a linear simulator, input and output circuits are designed so that the optimum load can be realized.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: June 18, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Sawai, Shigeyuki Murai, Tsutomu Yamaguchi, Yasoo Harada
  • Patent number: 5051373
    Abstract: An active device such as an HEMT is formed on a GaAs substrate, and characteristics of this active device formed are measured. A circuit pattern of a passive circuit device including a serial microstrip line is simulated on the basis of the results of this measurement, and a circuit pattern obtained by the simulation is directly drawn on a substrate to form the passive circuit device, thereby to fabricate an MMIC. Accordingly, the passive circuit device is formed in conformity with the characteristics of the active device for each chip.As a result, the variation in characteristics of the active device is canceled, to obtain an MMIC superior in matching.
    Type: Grant
    Filed: January 5, 1990
    Date of Patent: September 24, 1991
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Yamada, Akihito Nagamatsu, Seiichi Bamba, Tetsuro Sawai, Haruo Nakano, Kimihiko Nagami