Patents by Inventor Tetsuro Yamamoto

Tetsuro Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160284779
    Abstract: A display unit with which lowering of long-term reliability of a transistor is decreased is provided. The display unit includes a display section having a plurality of organic EL devices with light emitting color different from each other and a plurality of pixel circuits that are singly provided for every said organic EL device for every pixel. The pixel circuit has a first transistor for writing a video signal, a second transistor for driving the organic EL device based on the video signal written by the first transistor, and a retentive capacity, and out of the first transistor and the second transistor, a third transistor provided correspondingly to a second organic EL device adjacent to a first organic EL device is arranged farther from the first organic EL device than a first retentive capacity provided correspondingly to the second organic EL device out of the retentive capacity.
    Type: Application
    Filed: June 3, 2016
    Publication date: September 29, 2016
    Applicant: Sony Corporation
    Inventors: Takayuki Taneda, Tetsuro Yamamoto, Katsuhide Uchino
  • Patent number: 9454928
    Abstract: A pixel circuit having a function of compensating for characteristic variation of an electro-optical element and threshold voltage variation of a transistor is formed from a reduced number of component elements. An input signal is sampled from a signal line so as to be held in a holding capacitor. The threshold voltage of the drive transistor is imparted to the holding capacitor in order to cancel an influence of the threshold voltage.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: September 27, 2016
    Assignee: Sony Corporation
    Inventors: Katsuhide Uchino, Junichi Yamashita, Tetsuro Yamamoto
  • Patent number: 9454929
    Abstract: A pixel circuit having a function of compensating for characteristic variation of an electro-optical element and threshold voltage variation of a transistor is formed from a reduced number of component elements. An input signal is sampled from a signal line so as to be held in a holding capacitor. The threshold voltage of the drive transistor is imparted to the holding capacitor in order to cancel an influence of the threshold voltage.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: September 27, 2016
    Assignee: Sony Corporation
    Inventors: Katsuhide Uchino, Junichi Yamashita, Tetsuro Yamamoto
  • Patent number: 9437662
    Abstract: A display device including a pixel array having a plurality of pixels arranged in a matrix form, each of the pixels including a sampling transistor configured to sample a data potential from a video signal line which is insulated from and intersects a control line in response to the change in potential of the control line, and a light-emitting element configured to emit light at the brightness commensurate with the magnitude of the post-sampling data potential.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: September 6, 2016
    Assignee: SONY CORPORATION
    Inventors: Tetsuro Yamamoto, Katsuhide Uchino
  • Publication number: 20160253956
    Abstract: Disclosed herein is a display including: a pixel array part configured to include pixels that are arranged in a matrix and each have an electro-optical element, a write transistor for writing a video signal, a drive transistor for driving the electro-optical element based on the video signal written by the write transistor, and a holding capacitor connected between gate and source of the drive transistor, wherein the holding capacitor includes a first electrode, a second electrode disposed to face one surface of the first electrode for forming a first capacitor, and a third electrode disposed to face the other surface of the first electrode for forming a second capacitor, and the first capacitor and the second capacitor are connected in parallel to each other electrically.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 1, 2016
    Inventors: Hiroshi Sagawa, Katsuhide Uchino, Tetsuro Yamamoto
  • Patent number: 9385173
    Abstract: A display unit with which lowering of long-term reliability of a transistor is decreased is provided. The display unit includes a display section having a plurality of organic EL devices with light emitting color different from each other and a plurality of pixel circuits that are singly provided for every said organic EL device for every pixel. The pixel circuit has a first transistor for writing a video signal, a second transistor for driving the organic EL device based on the video signal written by the first transistor, and a retentive capacity, and out of the first transistor and the second transistor, a third transistor provided correspondingly to a second organic EL device adjacent to a first organic EL device is arranged farther from the first organic EL device than a first retentive capacity provided correspondingly to the second organic EL device out of the retentive capacity.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 5, 2016
    Assignee: Sony Corporation
    Inventors: Takayuki Taneda, Tetsuro Yamamoto, Katsuhide Uchino
  • Publication number: 20160125797
    Abstract: A pixel circuit having a function of compensating for characteristic variation of an electro-optical element and threshold voltage variation of a transistor is formed from a reduced number of component elements. An input signal is sampled from a signal line so as to be held in a holding capacitor. The threshold voltage of the drive transistor is imparted to the holding capacitor in order to cancel an influence of the threshold voltage.
    Type: Application
    Filed: January 13, 2016
    Publication date: May 5, 2016
    Inventors: Katsuhide Uchino, Junichi Yamashita, Tetsuro Yamamoto
  • Patent number: 9312315
    Abstract: Disclosed herein is a display including: a pixel array part configured to include pixels that are arranged in a matrix and each have an electro-optical element, a write transistor for writing a video signal, a drive transistor for driving the electro-optical element based on the video signal written by the write transistor, and a holding capacitor connected between gate and source of the drive transistor, wherein the holding capacitor includes a first electrode, a second electrode disposed to face one surface of the first electrode for forming a first capacitor, and a third electrode disposed to face the other surface of the first electrode for forming a second capacitor, and the first capacitor and the second capacitor are connected in parallel to each other electrically.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: April 12, 2016
    Assignee: Sony Corporation
    Inventors: Hiroshi Sagawa, Katsuhide Uchino, Tetsuro Yamamoto
  • Patent number: 9286828
    Abstract: A plurality of scanning periods are combined to form a composite period (2H). Within the first period of the front half, threshold value (Vth) correction is carried out all at once, and within the second period of the latter half, signal (Vsig) writing operation is carried out. High speed writing can be carried out even where the scanning period is shortened.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: March 15, 2016
    Assignee: JOLED Inc.
    Inventors: Tetsuro Yamamoto, Katsuhide Uchino
  • Patent number: 9286833
    Abstract: A buffer circuit includes a first transistor circuit having a first conductivity type transistor, a second transistor circuit having a second conductivity type transistors, in which the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively, in which at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and in which wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is included to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 15, 2016
    Assignee: JOLED Inc.
    Inventors: Tetsuro Yamamoto, Katsuhide Uchino
  • Patent number: 9287331
    Abstract: A display unit with which lowering of long-term reliability of a transistor is decreased is provided. The display unit includes a display section having a plurality of organic EL devices with light emitting color different from each other and a plurality of pixel circuits that are singly provided for every said organic EL device for every pixel. The pixel circuit has a first transistor for writing a video signal, a second transistor for driving the organic EL device based on the video signal written by the first transistor, and a retentive capacity, and out of the first transistor and the second transistor, a third transistor provided correspondingly to a second organic EL device adjacent to a first organic EL device is arranged farther from the first organic EL device than a first retentive capacity provided correspondingly to the second organic EL device out of the retentive capacity.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: March 15, 2016
    Assignee: Sony Corporation
    Inventors: Takayuki Taneda, Tetsuro Yamamoto, Katsuhide Uchino
  • Publication number: 20160071917
    Abstract: A display unit with which lowering of long-term reliability of a transistor is decreased is provided. The display unit includes a display section having a plurality of organic EL devices with light emitting color different from each other and a plurality of pixel circuits that are singly provided for every said organic EL device for every pixel. The pixel circuit has a first transistor for writing a video signal, a second transistor for driving the organic EL device based on the video signal written by the first transistor, and a retentive capacity, and out of the first transistor and the second transistor, a third transistor provided correspondingly to a second organic EL device adjacent to a first organic EL device is arranged farther from the first organic EL device than a first retentive capacity provided correspondingly to the second organic EL device out of the retentive capacity.
    Type: Application
    Filed: November 19, 2015
    Publication date: March 10, 2016
    Applicant: Sony Corporation
    Inventors: Takayuki Taneda, Tetsuro Yamamoto, Katsuhide Uchino
  • Publication number: 20160049456
    Abstract: Disclosed herein is a display apparatus, including: a plurality of subpixels disposed adjacent each other and forming one pixel which forms a unit for formation of a color image; the plurality of subpixels including a first subpixel which emits light of the shortest wavelength and a second subpixel disposed adjacent the first subpixel; the second subpixel having a light blocking member disposed between the second subpixel and the first subpixel and having a width greater than a channel length or a channel width of a transistor which forms the second subpixel.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 18, 2016
    Inventors: Tetsuro Yamamoto, Katsuhide Uchino
  • Patent number: 9263505
    Abstract: Disclosed herein is a display including: a pixel array part configured to include pixels that are arranged in a matrix, each having an electro-optical element, a write transistor for writing a video signal, a drive transistor for driving the electro-optical element based on the video signal written by the write transistor, and a holding capacitor connected between the gate and source of the drive transistor, wherein the holding capacitor includes a first electrode, a second electrode disposed to face one surface of the first electrode for forming a first capacitor, and a third electrode disposed to face the other surface of the first electrode for forming a second capacitor, and the first capacitor and the second capacitor are connected in parallel to each other electrically.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 16, 2016
    Assignee: Sony Corporation
    Inventors: Hiroshi Sagawa, Katsuhide Uchino, Tetsuro Yamamoto
  • Publication number: 20160005570
    Abstract: In one aspect, an ion implantation system is disclosed, which comprises a deceleration system configured to receive an ion beam and decelerate the ion beam at a deceleration ratio of at least 2, and an electrostatic bend disposed downstream of the deceleration system for causing a deflection of the ion beam. The electrostatic bend includes three tandem electrode pairs for receiving the decelerated beam, where each electrode pair has an inner and an outer electrode spaced apart to allow passage of the ion beam therethrough. Each of the electrodes of the end electrode pair is held at an electric potential less than an electric potential at which any of the electrodes of the middle electrode pair is held and the electrodes of the first electrode pair are held at a lower electric potential relative to the electrodes of the middle electrode pair.
    Type: Application
    Filed: August 20, 2015
    Publication date: January 7, 2016
    Inventors: Sami K. Hahto, Tetsuro Yamamoto
  • Patent number: 9230475
    Abstract: There is provided a display device including pixel circuits which are arranged and each of which includes a driving transistor to drive an electro-optical element and a capacitor connected between a gate electrode and one source/drain electrode of the driving transistor. The driving transistor is configured by stacking the gate electrode and the source/drain electrode and a peripheral portion of the gate electrode is covered by the source/drain electrode.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: January 5, 2016
    Assignee: JOLED Inc.
    Inventors: Tetsuro Yamamoto, Katsuhide Uchino
  • Publication number: 20150357391
    Abstract: A display device including a pixel array having a plurality of pixels arranged in a matrix form, each of the pixels including a sampling transistor configured to sample a data potential from a video signal line which is insulated from and intersects a control line in response to the change in potential of the control line, and a light-emitting element configured to emit light at the brightness commensurate with the magnitude of the post-sampling data potential.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 10, 2015
    Inventors: Tetsuro Yamamoto, Katsuhide Uchino
  • Publication number: 20150332657
    Abstract: An EL display panel including: a pixel array section in which EL display elements whose light emission state is controlled by an active matrix driving system are arranged in a form of a matrix; a first writing control line driving section and a second writing control line driving section configured to drive each writing control line from both sides of the pixel array section; and a first power supply line driving section and a second power supply line driving section configured to drive a power supply line disposed along a direction of a horizontal line from both sides of the pixel array section, the first power supply line driving section and the second power supply line driving section being respectively arranged between the first writing control line driving section and the pixel array section and between the second writing control line driving section and the pixel array section.
    Type: Application
    Filed: July 23, 2015
    Publication date: November 19, 2015
    Inventors: Tetsuro Yamamoto, Katsuhide Uchino, Masakazu Kato
  • Publication number: 20150302800
    Abstract: A pixel circuit able to prevent a spread of the terminal voltages of drive transistors inside a panel and in turn able to reliably prevent deterioration of uniformity, wherein a source of a TFT serving as a drive transistor is connected to an anode of a light emitting element, a drain is connected to a power source potential, a capacitor is connected between a gate and source of the TFT, and a source potential of the TFT is connected to a fixed potential through a TFT serving as a switch transistor and wherein pixel circuit lines are connected by an upper line and bottom line and are arranged in parallel with pixel circuit power source voltage lines so as not to have intersecting parts.
    Type: Application
    Filed: July 1, 2015
    Publication date: October 22, 2015
    Applicant: Sony Corporation
    Inventors: Katsuhide UCHINO, Juichi Yamashita, Tetsuro Yamamoto
  • Publication number: 20150294623
    Abstract: A display unit includes: a unit pixel; a switch configured to perform ON-OFF control between a second terminal and a third terminal, based on a pulse signal applied to a first terminal, the second terminal being supplied with a DC signal, and the third terminal being connected to the unit pixel; and a non-linear element interposed between the first terminal and the third terminal.
    Type: Application
    Filed: December 18, 2013
    Publication date: October 15, 2015
    Applicant: JOLED INC.
    Inventors: Naobumi Toyomura, Tetsuro Yamamoto